rk3368: efuse: change efuse get temp func

[firefly-linux-kernel-4.4.55.git] / arch / arm / Kconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 976d7c0ef24b58cb8553fc15c44e897d659c14aa..67a7acc911829e30b0f21365af306f17a280e7bd 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -48,6 +48,7 @@ config ARM
        select HAVE_MEMBLOCK
        select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
        select HAVE_PERF_EVENTS
+       select HAVE_PIE
        select HAVE_REGS_AND_STACK_ACCESS_API
        select HAVE_SYSCALL_TRACEPOINTS
        select HAVE_UID16
@@ -983,6 +984,8 @@ source "arch/arm/mach-mmp/Kconfig"
 
 source "arch/arm/mach-realview/Kconfig"
 
+source "arch/arm/mach-rockchip/Kconfig"
+
 source "arch/arm/mach-sa1100/Kconfig"
 
 source "arch/arm/plat-samsung/Kconfig"
@@ -1358,6 +1361,29 @@ config ARM_ERRATA_798181
          which sends an IPI to the CPUs that are running the same ASID
          as the one being invalidated.
 
+config ARM_ERRATA_818325
+       bool "ARM errata: Execution of an UNPREDICTABLE STR or STM instruction might deadlock"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 818325 Cortex-A12
+         (r0p0..r0p1-00lac0-rc11) erratum. When a CPU executes a sequence of
+         two conditional store instructions with opposite condition code and
+         updating the same register, the system might enter a deadlock if the
+         second conditional instruction is an UNPREDICTABLE STR or STM
+         instruction. This workaround setting bit[12] of the Feature Register
+         prevents the erratum. This bit disables an optimisation applied to a
+         sequence of 2 instructions that use opposing condition codes.
+
+config ARM_ERRATA_821420
+       bool "ARM errata: A sequence of VMOV to core registers instruction might lead to a deadlock"
+       depends on CPU_V7
+       help
+         This option enables the workaround for the 821420 Cortex-A12 (r0p0,
+         r0p1) erratum. In very rare timing conditions, a sequence of VMOV to
+         Core registers instructions, for which the second one is in the
+         shadow of a branch or abort, can lead to a deadlock when the VMOV
+         instructions are issued out-of-order.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1714,6 +1740,7 @@ config ARCH_NR_GPIO
        int
        default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
        default 512 if SOC_OMAP5
+       default 512 if ARCH_ROCKCHIP
        default 392 if ARCH_U8500
        default 352 if ARCH_VT8500
        default 288 if ARCH_SUNXI
@@ -2359,6 +2386,13 @@ config NEON
          Say Y to include support code for NEON, the ARMv7 Advanced SIMD
          Extension.
 
+config KERNEL_MODE_NEON
+       bool "Support for NEON in kernel mode"
+       default n
+       depends on NEON
+       help
+         Say Y to include support for NEON in kernel mode.
+
 endmenu
 
 menu "Userspace binary formats"