select RK_PL330_DMA
select MIGHT_HAVE_CACHE_L2X0
select ARM_ERRATA_754322
+ select ARM_ERRATA_775420
help
Support for Rockchip's RK2928 SoCs.
+config ARCH_RK3026
+ bool "Rockchip RK3026/RK3028A"
+ select PLAT_RK
+ select CPU_V7
+ select ARM_GIC
+ select RK_PL330_DMA
+ select RK_TIMER
+ select HAVE_ARM_TWD if LOCAL_TIMERS
+ select HAVE_SMP
+ select MIGHT_HAVE_CACHE_L2X0
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_764369
+ help
+ Support for Rockchip's RK3026/RK3028A SoCs.
+
config ARCH_RK30
- bool "Rockchip RK30xx"
+ bool "Rockchip RK30xx/RK3108/RK3168"
select PLAT_RK
select CPU_V7
select ARM_GIC
select MIGHT_HAVE_CACHE_L2X0
select ARM_ERRATA_764369
select ARM_ERRATA_754322
+ select ARM_ERRATA_775420
help
- Support for Rockchip's RK30xx SoCs.
+ Support for Rockchip's RK30xx/RK3108/RK3168 SoCs.
-config ARCH_RK31
- bool "Rockchip RK31xx"
+config ARCH_RK3188
+ bool "Rockchip RK3188"
select PLAT_RK
select CPU_V7
select ARM_GIC
select RK_PL330_DMA
+ select RK_TIMER
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
+ select ARM_ERRATA_761320
select ARM_ERRATA_764369
select ARM_ERRATA_754322
+ select ARM_ERRATA_775420
+ help
+ Support for Rockchip's RK3188 SoCs.
+
+config ARCH_RK319X
+ bool "Rockchip RK319X"
+ select PLAT_RK
+ select CPU_V7
+ select ARM_GIC
+ select RK_PL330_DMA
+ select RK_TIMER
+ select HAVE_SMP
+ select MIGHT_HAVE_CACHE_L2X0
+ select ARM_ERRATA_761320 if SMP
+ select ARM_ERRATA_764369 if SMP
+ select ARM_ERRATA_754322
+ select ARM_ERRATA_775420
help
- Support for Rockchip's RK31xx SoCs.
+ Support for Rockchip's RK319X SoCs.
config PLAT_SPEAR
bool "ST SPEAr"
source "arch/arm/plat-rk/Kconfig"
source "arch/arm/mach-rk29/Kconfig"
source "arch/arm/mach-rk2928/Kconfig"
+source "arch/arm/mach-rk3026/Kconfig"
source "arch/arm/mach-rk30/Kconfig"
+source "arch/arm/mach-rk3188/Kconfig"
+source "arch/arm/mach-rk319x/Kconfig"
source "arch/arm/mach-sa1100/Kconfig"
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
+ select SYNC
+ select SW_SYNC
+ select SW_SYNC_USER
config PLAT_VERSATILE
bool
This workaround defines cpu_relax() as smp_mb(), preventing correctly
written polling loops from denying visibility of updates to memory.
+config ARM_ERRATA_761320
+ bool "ARM errata: no direct eviction"
+ depends on CPU_V7 && SMP
+ help
+ This option enables the workaround for the 761320 Cortex-A9 erratum.
+
+config ARM_ERRATA_764369
+ bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
+ depends on CPU_V7 && SMP
+ help
+ This option enables the workaround for erratum 764369
+ affecting Cortex-A9 MPCore with two or more processors (all
+ current revisions). Under certain timing circumstances, a data
+ cache line maintenance operation by MVA targeting an Inner
+ Shareable memory region may fail to proceed up to either the
+ Point of Coherency or to the Point of Unification of the
+ system. This workaround adds a DSB instruction before the
+ relevant cache maintenance functions and sets a specific bit
+ in the diagnostic control register of the SCU.
+
+config PL310_ERRATA_769419
+ bool "PL310 errata: no automatic Store Buffer drain"
+ depends on CACHE_L2X0
+ help
+ On revisions of the PL310 prior to r3p2, the Store Buffer does
+ not automatically drain. This can cause normal, non-cacheable
+ writes to be retained when the memory system is idle, leading
+ to suboptimal I/O performance for drivers using coherent DMA.
+ This option adds a write barrier to the cpu_idle loop so that,
+ on systems with an outer cache, the store buffer is drained
+ explicitly.
+
+config ARM_ERRATA_775420
+ bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
+ depends on CPU_V7
+ help
+ This option enables the workaround for the 775420 Cortex-A9 (r2p2,
+ r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
+ operation aborts with MMU exception, it might cause the processor
+ to deadlock. This workaround puts DSB before executing ISB if
+ an abort may occur on cache maintenance.
+
endmenu
source "arch/arm/common/Kconfig"
source "drivers/pcmcia/Kconfig"
-config ARM_ERRATA_764369
- bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
- depends on CPU_V7 && SMP
- help
- This option enables the workaround for erratum 764369
- affecting Cortex-A9 MPCore with two or more processors (all
- current revisions). Under certain timing circumstances, a data
- cache line maintenance operation by MVA targeting an Inner
- Shareable memory region may fail to proceed up to either the
- Point of Coherency or to the Point of Unification of the
- system. This workaround adds a DSB instruction before the
- relevant cache maintenance functions and sets a specific bit
- in the diagnostic control register of the SCU.
-
-config PL310_ERRATA_769419
- bool "PL310 errata: no automatic Store Buffer drain"
- depends on CACHE_L2X0
- help
- On revisions of the PL310 prior to r3p2, the Store Buffer does
- not automatically drain. This can cause normal, non-cacheable
- writes to be retained when the memory system is idle, leading
- to suboptimal I/O performance for drivers using coherent DMA.
- This option adds a write barrier to the cpu_idle loop so that,
- on systems with an outer cache, the store buffer is drained
- explicitly.
-
endmenu
menu "Kernel Features"
bool "Use local timer interrupts"
depends on SMP
default y
- select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
+ select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT && !RK_TIMER)
help
Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system
config CPU_FREQ_IMX
tristate "CPUfreq driver for i.MX CPUs"
depends on ARCH_MXC && CPU_FREQ
+ select CPU_FREQ_TABLE
help
This enables the CPUfreq driver for i.MX CPUs.
projects / firefly-linux-kernel-4.4.55.git / blobdiff