model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
+ L2: l2-cache {
+ compatible = "marvell,aurora-system-cache";
+ reg = <0xd0008000 0x1000>;
+ cache-id-part = <0x100>;
+ wt-override;
+ };
+
mpic: interrupt-controller@d0020000 {
reg = <0xd0020a00 0x1d0>,
- <0xd0021870 0x58>;
+ <0xd0021070 0x58>;
+ };
+
+ armada-370-xp-pmsu@d0022000 {
+ compatible = "marvell,armada-370-xp-pmsu";
+ reg = <0xd0022100 0x430>,
+ <0xd0020800 0x20>;
};
soc {
serial@d0012200 {
- compatible = "ns16550";
+ compatible = "snps,dw-apb-uart";
reg = <0xd0012200 0x100>;
reg-shift = <2>;
interrupts = <43>;
+ reg-io-width = <4>;
status = "disabled";
};
serial@d0012300 {
- compatible = "ns16550";
+ compatible = "snps,dw-apb-uart";
reg = <0xd0012300 0x100>;
reg-shift = <2>;
interrupts = <44>;
+ reg-io-width = <4>;
status = "disabled";
};
clocks = <&gateclk 1>;
status = "disabled";
};
+
+ xor@d0060900 {
+ compatible = "marvell,orion-xor";
+ reg = <0xd0060900 0x100
+ 0xd0060b00 0x100>;
+ clocks = <&gateclk 22>;
+ status = "okay";
+
+ xor10 {
+ interrupts = <51>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor11 {
+ interrupts = <52>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+ };
+
+ xor@d00f0900 {
+ compatible = "marvell,orion-xor";
+ reg = <0xd00F0900 0x100
+ 0xd00F0B00 0x100>;
+ clocks = <&gateclk 28>;
+ status = "okay";
+
+ xor00 {
+ interrupts = <94>;
+ dmacap,memcpy;
+ dmacap,xor;
+ };
+ xor01 {
+ interrupts = <95>;
+ dmacap,memcpy;
+ dmacap,xor;
+ dmacap,memset;
+ };
+ };
};
};