Merge tag 'v3.17-rockchip-rk3288' of git://git.kernel.org/pub/scm/linux/kernel/git...

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / dra7xx-clocks.dtsi

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index c7676871d9c0240032261ed40f0db7c431a583d8..2c05b3f017fa22ec4370c02e80fc390a65ed8772 100644 (file)
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -10,26 +10,26 @@
 &cm_core_aon_clocks {
        atl_clkin0_ck: atl_clkin0_ck {
                #clock-cells = <0>;
-               compatible = "fixed-clock";
-               clock-frequency = <0>;
+               compatible = "ti,dra7-atl-clock";
+               clocks = <&atl_gfclk_mux>;
        };
 
        atl_clkin1_ck: atl_clkin1_ck {
                #clock-cells = <0>;
-               compatible = "fixed-clock";
-               clock-frequency = <0>;
+               compatible = "ti,dra7-atl-clock";
+               clocks = <&atl_gfclk_mux>;
        };
 
        atl_clkin2_ck: atl_clkin2_ck {
                #clock-cells = <0>;
-               compatible = "fixed-clock";
-               clock-frequency = <0>;
+               compatible = "ti,dra7-atl-clock";
+               clocks = <&atl_gfclk_mux>;
        };
 
-       atlclkin3_ck: atlclkin3_ck {
+       atl_clkin3_ck: atl_clkin3_ck {
                #clock-cells = <0>;
-               compatible = "fixed-clock";
-               clock-frequency = <0>;
+               compatible = "ti,dra7-atl-clock";
+               clocks = <&atl_gfclk_mux>;
        };
 
        hdmi_clkin_ck: hdmi_clkin_ck {
@@ -277,7 +277,7 @@
 
        dpll_mpu_ck: dpll_mpu_ck {
                #clock-cells = <0>;
-               compatible = "ti,omap4-dpll-clock";
+               compatible = "ti,omap5-mpu-dpll-clock";
                clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
                reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
        };
@@ -673,10 +673,12 @@
 
        l3_iclk_div: l3_iclk_div {
                #clock-cells = <0>;
-               compatible = "fixed-factor-clock";
+               compatible = "ti,divider-clock";
+               ti,max-div = <2>;
+               ti,bit-shift = <4>;
+               reg = <0x0100>;
                clocks = <&dpll_core_h12x2_ck>;
-               clock-mult = <1>;
-               clock-div = <1>;
+               ti,index-power-of-two;
        };
 
        l4_root_clk_div: l4_root_clk_div {
@@ -684,7 +686,7 @@
                compatible = "fixed-factor-clock";
                clocks = <&l3_iclk_div>;
                clock-mult = <1>;
-               clock-div = <1>;
+               clock-div = <2>;
        };
 
        video1_clk2_div: video1_clk2_div {
@@ -730,7 +732,7 @@
        mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
                ti,bit-shift = <28>;
                reg = <0x0550>;
        };
@@ -738,7 +740,7 @@
        mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
                ti,bit-shift = <24>;
                reg = <0x0550>;
        };
@@ -1152,7 +1154,7 @@
 
        apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
                compatible = "ti,mux-clock";
-               clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+               clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
                #clock-cells = <0>;
                reg = <0x021c 0x4>;
                ti,bit-shift = <7>;
@@ -1165,16 +1167,33 @@
                reg = <0x021c>, <0x0220>;
        };
 
+       optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
+               compatible = "ti,gate-clock";
+               clocks = <&sys_32k_ck>;
+               #clock-cells = <0>;
+               reg = <0x13b0>;
+               ti,bit-shift = <8>;
+       };
+
+       optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
+               compatible = "ti,gate-clock";
+               clocks = <&sys_32k_ck>;
+               #clock-cells = <0>;
+               reg = <0x13b8>;
+               ti,bit-shift = <8>;
+       };
+
        optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
                compatible = "ti,divider-clock";
                clocks = <&apll_pcie_ck>;
                #clock-cells = <0>;
                reg = <0x021c>;
+               ti,dividers = <2>, <1>;
                ti,bit-shift = <8>;
                ti,max-div = <2>;
        };
 
-       optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+       optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
                compatible = "ti,gate-clock";
                clocks = <&apll_pcie_ck>;
                #clock-cells = <0>;
@@ -1182,7 +1201,15 @@
                ti,bit-shift = <9>;
        };
 
-       optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+       optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
+               compatible = "ti,gate-clock";
+               clocks = <&apll_pcie_ck>;
+               #clock-cells = <0>;
+               reg = <0x13b8>;
+               ti,bit-shift = <9>;
+       };
+
+       optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
                compatible = "ti,gate-clock";
                clocks = <&optfclk_pciephy_div>;
                #clock-cells = <0>;
@@ -1190,6 +1217,14 @@
                ti,bit-shift = <10>;
        };
 
+       optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
+               compatible = "ti,gate-clock";
+               clocks = <&optfclk_pciephy_div>;
+               #clock-cells = <0>;
+               reg = <0x13b8>;
+               ti,bit-shift = <10>;
+       };
+
        apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
@@ -1639,7 +1674,7 @@
        mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
                ti,bit-shift = <28>;
                reg = <0x1860>;
        };
@@ -1647,7 +1682,7 @@
        mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
                ti,bit-shift = <24>;
                reg = <0x1860>;
        };
@@ -1663,7 +1698,7 @@
        mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
                ti,bit-shift = <24>;
                reg = <0x1868>;
        };
@@ -1679,7 +1714,7 @@
        mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
                ti,bit-shift = <24>;
                reg = <0x1898>;
        };
@@ -1695,7 +1730,7 @@
        mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
                ti,bit-shift = <24>;
                reg = <0x1878>;
        };
@@ -1711,7 +1746,7 @@
        mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
                ti,bit-shift = <24>;
                reg = <0x1904>;
        };
@@ -1727,7 +1762,7 @@
        mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
                ti,bit-shift = <24>;
                reg = <0x1908>;
        };
@@ -1743,7 +1778,7 @@
        mcasp8_ahclk_mux: mcasp8_ahclk_mux {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
-               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+               clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
                ti,bit-shift = <22>;
                reg = <0x1890>;
        };