soc: rockchip: rename rockchip_boot-mode.h to rockchip,boot-mode.h

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / rk3288.dtsi

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 01c01979fa816f838a8fdddd3ef46e71f5b6e356..09c67c9f5d5e73ebc43a3623c45334fdf37e5be2 100644 (file)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -45,7 +45,7 @@
 #include <dt-bindings/clock/rk3288-cru.h>
 #include <dt-bindings/thermal/thermal.h>
 #include <dt-bindings/power/rk3288-power.h>
-#include <dt-bindings/soc/rockchip_boot-mode.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
 #include "skeleton.dtsi"
 
 / {
@@ -54,6 +54,7 @@
        interrupt-parent = <&gic>;
 
        aliases {
+               ethernet0 = &gmac;
                i2c0 = &i2c0;
                i2c1 = &i2c1;
                i2c2 = &i2c2;
@@ -1010,6 +1011,20 @@
                status = "disabled";
        };
 
+       rga: rga@ff920000 {
+               compatible = "rockchip,rk3288-rga";
+               reg = <0xff920000 0x180>;
+               interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "rga";
+               clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+               clock-names = "aclk", "hclk", "sclk";
+
+               resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
+
+               reset-names = "core", "axi", "ahb";
+               status = "disabled";
+       };
+
        vopb: vop@ff930000 {
                compatible = "rockchip,rk3288-vop";
                reg = <0xff930000 0x19c>;
@@ -1284,6 +1299,8 @@
                iommu_enabled = <1>;
                dev_mode = <0>;
                status = "disabled";
+               /* 0 means ion, 1 means drm */
+               allocator = <1>;
        };
 
        vpu_mmu: iommu@ff9a0800 {
@@ -1323,6 +1340,8 @@
                iommus = <&hevc_mmu>;
                iommu_enabled = <1>;
                status = "disabled";
+               /* 0 means ion, 1 means drm */
+               allocator = <1>;
        };
 
        hevc_mmu: iommu@ff9c0440 {