#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/power/rk3288-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/display/drm_mipi_dsi.h>
#include "skeleton.dtsi"
/ {
status = "disabled";
};
+ i2c0: i2c@ff650000 {
+ compatible = "rockchip,rk3288-i2c";
+ reg = <0xff650000 0x1000>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ status = "disabled";
+ };
+
i2c1: i2c@ff140000 {
compatible = "rockchip,rk3288-i2c";
reg = <0xff140000 0x1000>;
"aclk_mac", "pclk_mac";
resets = <&cru SRST_MAC>;
reset-names = "stmmaceth";
- max-speed = <100>;
status = "disabled";
};
"arm_clk", "aclk_dmac1";
};
- i2c0: i2c@ff650000 {
- compatible = "rockchip,rk3288-i2c";
- reg = <0xff650000 0x1000>;
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "i2c";
- clocks = <&cru PCLK_I2C0>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_xfer>;
- status = "disabled";
- };
-
i2c2: i2c@ff660000 {
compatible = "rockchip,rk3288-i2c";
reg = <0xff660000 0x1000>;
status = "disabled";
};
+ cif_isp0: cif_isp@ff910000 {
+ compatible = "rockchip,rk3288-cif-isp";
+ rockchip,grf = <&grf>;
+ reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
+ reg-names = "register", "csihost-register";
+ clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
+ <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
+ <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
+ <&cru SCLK_MIPIDSI_24M>;
+ clock-names = "aclk_isp", "hclk_isp",
+ "sclk_isp", "sclk_isp_jpe",
+ "pclk_mipi_csi", "pclk_isp_in",
+ "sclk_mipidsi_24m";
+ resets = <&cru SRST_ISP>;
+ reset-names = "rst_isp";
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cif_isp10_irq";
+ status = "disabled";
+ };
+
rga: rga@ff920000 {
compatible = "rockchip,rk3288-rga";
reg = <0xff920000 0x180>;
power-domains = <&power RK3288_PD_VIO>;
resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
reset-names = "core", "axi", "ahb";
+ dma-coherent;
status = "disabled";
};
reg = <0xff930300 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopb_mmu";
+ clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
+ clock-names = "aclk", "hclk";
power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
reg = <0xff940300 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
+ clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+ clock-names = "aclk", "hclk";
power-domains = <&power RK3288_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
clock-names = "iahb", "isfr";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_ddc>;
power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
};
};
- gpu: gpu@ffa30000 {
- compatible = "arm,malit764",
- "arm,malit76x",
- "arm,malit7xx",
- "arm,mali-midgard";
- reg = <0xffa30000 0x10000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "JOB", "MMU", "GPU";
- clocks = <&cru ACLK_GPU>;
- clock-names = "clk_mali";
- operating-points-v2 = <&gpu_opp_table>;
- #cooling-cells = <2>; /* min followed by max */
- power-domains = <&power RK3288_PD_GPU>;
- status = "disabled";
-
- gpu_power_model: power_model {
- compatible = "arm,mali-simple-power-model";
- voltage = <950>;
- frequency = <500>;
- static-power = <300>;
- dynamic-power = <396>;
- ts = <32000 4700 (-80) 2>;
- thermal-zone = "gpu_thermal";
- };
- };
-
- gpu_opp_table: opp-table1 {
- compatible = "operating-points-v2";
-
- opp@100000000 {
- opp-hz = /bits/ 64 <100000000>;
- opp-microvolt = <950000>;
- };
- opp@200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <950000>;
- };
- opp@300000000 {
- opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <1000000>;
- };
- opp@400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <1100000>;
- };
- opp@600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1250000>;
- };
- };
-
- noc: syscon@ffac0000 {
- compatible = "rockchip,rk3288-noc", "syscon";
- reg = <0xffac0000 0x2000>;
- };
-
vpu: video-codec@ff9a0000 {
compatible = "rockchip,rk3288-vpu";
reg = <0xff9a0000 0x800>;
reg = <0xff9a0800 0x100>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "hclk";
power-domains = <&power RK3288_PD_VIDEO>;
#iommu-cells = <0>;
};
reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
+ <&cru SCLK_HEVC_CORE>,
+ <&cru SCLK_HEVC_CABAC>;
+ clock-names = "aclk", "hclk", "clk_core",
+ "clk_cabac";
power-domains = <&power RK3288_PD_HEVC>;
#iommu-cells = <0>;
};
- gic: interrupt-controller@ffc01000 {
- compatible = "arm,gic-400";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <0>;
+ gpu: gpu@ffa30000 {
+ compatible = "arm,malit764",
+ "arm,malit76x",
+ "arm,malit7xx",
+ "arm,mali-midgard";
+ reg = <0xffa30000 0x10000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "JOB", "MMU", "GPU";
+ clocks = <&cru ACLK_GPU>;
+ clock-names = "clk_mali";
+ operating-points-v2 = <&gpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ power-domains = <&power RK3288_PD_GPU>;
+ status = "disabled";
- reg = <0xffc01000 0x1000>,
- <0xffc02000 0x1000>,
- <0xffc04000 0x2000>,
- <0xffc06000 0x2000>;
- interrupts = <GIC_PPI 9 0xf04>;
+ upthreshold = <75>;
+ downdifferential = <10>;
+
+ gpu_power_model: power_model {
+ compatible = "arm,mali-simple-power-model";
+ voltage = <950>;
+ frequency = <500>;
+ static-power = <300>;
+ dynamic-power = <396>;
+ ts = <32000 4700 (-80) 2>;
+ thermal-zone = "gpu_thermal";
+ };
+ };
+
+ gpu_opp_table: opp-table1 {
+ compatible = "operating-points-v2";
+
+ opp@100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <950000>;
+ };
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp@300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1250000>;
+ };
+ };
+
+ noc: syscon@ffac0000 {
+ compatible = "rockchip,rk3288-noc", "syscon";
+ reg = <0xffac0000 0x2000>;
};
efuse: efuse@ffb40000 {
};
};
- cif_isp0: cif_isp@ff910000 {
- compatible = "rockchip,rk3288-cif-isp";
- rockchip,grf = <&grf>;
- reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
- reg-names = "register", "csihost-register";
- clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
- <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
- <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
- <&cru SCLK_MIPIDSI_24M>;
- clock-names = "aclk_isp", "hclk_isp",
- "sclk_isp", "sclk_isp_jpe",
- "pclk_mipi_csi", "pclk_isp_in",
- "sclk_mipidsi_24m";
- resets = <&cru SRST_ISP>;
- reset-names = "rst_isp";
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cif_isp10_irq";
- status = "disabled";
+ gic: interrupt-controller@ffc01000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0xffc01000 0x1000>,
+ <0xffc02000 0x1000>,
+ <0xffc04000 0x2000>,
+ <0xffc06000 0x2000>;
+ interrupts = <GIC_PPI 9 0xf04>;
};
pinctrl: pinctrl {
projects / firefly-linux-kernel-4.4.55.git / blobdiff