/ {
interrupt-parent = <&gic>;
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ #clock-cells = <0>;
+ clock-output-names = "xin24m";
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,cortex-a9-global-timer";
reg = <0x1013c200 0x20>;
interrupts = <GIC_PPI 11 0x304>;
- clocks = <&dummy150m>;
+ clocks = <&cru CORE_PERI>;
};
local-timer@1013c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x1013c600 0x20>;
interrupts = <GIC_PPI 13 0x304>;
- clocks = <&dummy150m>;
+ clocks = <&cru CORE_PERI>;
};
uart0: serial@10124000 {
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
- clocks = <&clk_gates1 8>;
+ clocks = <&cru SCLK_UART0>;
status = "disabled";
};
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
- clocks = <&clk_gates1 10>;
+ clocks = <&cru SCLK_UART1>;
status = "disabled";
};
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
- clocks = <&clk_gates1 12>;
+ clocks = <&cru SCLK_UART2>;
status = "disabled";
};
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
- clocks = <&clk_gates1 14>;
+ clocks = <&cru SCLK_UART3>;
status = "disabled";
};
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clk_gates5 10>, <&clk_gates2 11>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
clock-names = "biu", "ciu";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clk_gates5 11>, <&clk_gates2 13>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
clock-names = "biu", "ciu";
status = "disabled";