Merge tag 'armsoc-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / ste-dbx5x0.dtsi

diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index 2201cd5da3bb95843278b27c8f855d540d154041..853684ad777337771b48be2982a7c525f95ef1d6 100644 (file)
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -22,6 +22,160 @@
                interrupt-parent = <&intc>;
                ranges;
 
+               cpus {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       cpu-map {
+                               cluster0 {
+                                       core0 {
+                                               cpu = <&CPU0>;
+                                       };
+                                       core1 {
+                                               cpu = <&CPU1>;
+                                       };
+                               };
+                       };
+                       CPU0: cpu@0 {
+                               device_type = "cpu";
+                               compatible = "arm,cortex-a9";
+                               reg = <0>;
+                       };
+                       CPU1: cpu@1 {
+                               device_type = "cpu";
+                               compatible = "arm,cortex-a9";
+                               reg = <1>;
+                       };
+               };
+
+               ptm@801ae000 {
+                       compatible = "arm,coresight-etm3x", "arm,primecell";
+                       reg = <0x801ae000 0x1000>;
+
+                       clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
+                       clock-names = "apb_pclk", "atclk";
+                       cpu = <&CPU0>;
+                       port {
+                               ptm0_out_port: endpoint {
+                                       remote-endpoint = <&funnel_in_port0>;
+                               };
+                       };
+               };
+
+               ptm@801af000 {
+                       compatible = "arm,coresight-etm3x", "arm,primecell";
+                       reg = <0x801af000 0x1000>;
+
+                       clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
+                       clock-names = "apb_pclk", "atclk";
+                       cpu = <&CPU1>;
+                       port {
+                               ptm1_out_port: endpoint {
+                                       remote-endpoint = <&funnel_in_port1>;
+                               };
+                       };
+               };
+
+               funnel@801a6000 {
+                       compatible = "arm,coresight-funnel", "arm,primecell";
+                       reg = <0x801a6000 0x1000>;
+
+                       clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
+                       clock-names = "apb_pclk", "atclk";
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               /* funnel output ports */
+                               port@0 {
+                                       reg = <0>;
+                                       funnel_out_port: endpoint {
+                                               remote-endpoint =
+                                                       <&replicator_in_port0>;
+                                       };
+                               };
+
+                               /* funnel input ports */
+                               port@1 {
+                                       reg = <0>;
+                                       funnel_in_port0: endpoint {
+                                               slave-mode;
+                                               remote-endpoint = <&ptm0_out_port>;
+                                       };
+                               };
+
+                               port@2 {
+                                       reg = <1>;
+                                       funnel_in_port1: endpoint {
+                                               slave-mode;
+                                               remote-endpoint = <&ptm1_out_port>;
+                                       };
+                               };
+                       };
+               };
+
+               replicator {
+                       compatible = "arm,coresight-replicator";
+                       clocks = <&prcmu_clk PRCMU_APEATCLK>;
+                       clock-names = "atclk";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               /* replicator output ports */
+                               port@0 {
+                                       reg = <0>;
+                                       replicator_out_port0: endpoint {
+                                               remote-endpoint = <&tpiu_in_port>;
+                                       };
+                               };
+                               port@1 {
+                                       reg = <1>;
+                                       replicator_out_port1: endpoint {
+                                               remote-endpoint = <&etb_in_port>;
+                                       };
+                               };
+
+                               /* replicator input port */
+                               port@2 {
+                                       reg = <0>;
+                                       replicator_in_port0: endpoint {
+                                               slave-mode;
+                                               remote-endpoint = <&funnel_out_port>;
+                                       };
+                               };
+                       };
+               };
+
+               tpiu@80190000 {
+                       compatible = "arm,coresight-tpiu", "arm,primecell";
+                       reg = <0x80190000 0x1000>;
+
+                       clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
+                       clock-names = "apb_pclk", "atclk";
+                       port {
+                               tpiu_in_port: endpoint {
+                                       slave-mode;
+                                       remote-endpoint = <&replicator_out_port0>;
+                               };
+                       };
+               };
+
+               etb@801a4000 {
+                       compatible = "arm,coresight-etb10", "arm,primecell";
+                       reg = <0x801a4000 0x1000>;
+
+                       clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
+                       clock-names = "apb_pclk", "atclk";
+                       port {
+                               etb_in_port: endpoint {
+                                       slave-mode;
+                                       remote-endpoint = <&replicator_out_port1>;
+                               };
+                       };
+               };
+
                intc: interrupt-controller@a0411000 {
                        compatible = "arm,cortex-a9-gic";
                        #interrupt-cells = <3>;
@@ -31,6 +185,20 @@
                              <0xa0410100 0x100>;
                };
 
+               scu@a04100000 {
+                       compatible = "arm,cortex-a9-scu";
+                       reg = <0xa0410000 0x100>;
+               };
+
+               /*
+                * The backup RAM is used for retention during sleep
+                * and various things like spin tables
+                */
+               backupram@80150000 {
+                       compatible = "ste,dbx500-backupram";
+                       reg = <0x80150000 0x2000>;
+               };
+
                L2: l2-cache {
                        compatible = "arm,pl310-cache";
                        reg = <0xa0412000 0x1000>;
@@ -91,6 +259,13 @@
                        clocks = <&smp_twd_clk>;
                };
 
+               watchdog@a0410620 {
+                       compatible = "arm,cortex-a9-twd-wdt";
+                       reg = <0xa0410620 0x20>;
+                       interrupts = <1 14 0x304>;
+                       clocks = <&smp_twd_clk>;
+               };
+
                rtc@80154000 {
                        compatible = "arm,rtc-pl031", "arm,primecell";
                        reg = <0x80154000 0x1000>;