Merge tag 'v3.17-rockchip-rk3288' of git://git.kernel.org/pub/scm/linux/kernel/git...

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / sun6i-a31.dtsi

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index baf8eff5761023fb6f9ff446088153691f968d6b..44b07e512c2448cbc24821668dc43ceaf6915638 100644 (file)
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -23,6 +23,7 @@
                serial3 = &uart3;
                serial4 = &uart4;
                serial5 = &uart5;
+               ethernet0 = &gmac;
        };
 
 
@@ -281,6 +282,34 @@
                                             "usb_ohci0", "usb_ohci1",
                                             "usb_ohci2";
                };
+
+               /*
+                * The following two are dummy clocks, placeholders used in the gmac_tx
+                * clock. The gmac driver will choose one parent depending on the PHY
+                * interface mode, using clk_set_rate auto-reparenting.
+                * The actual TX clock rate is not controlled by the gmac_tx clock.
+                */
+               mii_phy_tx_clk: clk@1 {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <25000000>;
+                       clock-output-names = "mii_phy_tx";
+               };
+
+               gmac_int_tx_clk: clk@2 {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <125000000>;
+                       clock-output-names = "gmac_int_tx";
+               };
+
+               gmac_tx_clk: clk@01c200d0 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun7i-a20-gmac-clk";
+                       reg = <0x01c200d0 0x4>;
+                       clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+                       clock-output-names = "gmac_tx";
+               };
        };
 
        soc@01c00000 {
@@ -467,6 +496,48 @@
                                allwinner,drive = <2>;
                                allwinner,pull = <0>;
                        };
+
+                       gmac_pins_mii_a: gmac_mii@0 {
+                               allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+                                               "PA8", "PA9", "PA11",
+                                               "PA12", "PA13", "PA14", "PA19",
+                                               "PA20", "PA21", "PA22", "PA23",
+                                               "PA24", "PA26", "PA27";
+                               allwinner,function = "gmac";
+                               allwinner,drive = <0>;
+                               allwinner,pull = <0>;
+                       };
+
+                       gmac_pins_gmii_a: gmac_gmii@0 {
+                               allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+                                               "PA4", "PA5", "PA6", "PA7",
+                                               "PA8", "PA9", "PA10", "PA11",
+                                               "PA12", "PA13", "PA14", "PA15",
+                                               "PA16", "PA17", "PA18", "PA19",
+                                               "PA20", "PA21", "PA22", "PA23",
+                                               "PA24", "PA25", "PA26", "PA27";
+                               allwinner,function = "gmac";
+                               /*
+                                * data lines in GMII mode run at 125MHz and
+                                * might need a higher signal drive strength
+                                */
+                               allwinner,drive = <2>;
+                               allwinner,pull = <0>;
+                       };
+
+                       gmac_pins_rgmii_a: gmac_rgmii@0 {
+                               allwinner,pins = "PA0", "PA1", "PA2", "PA3",
+                                               "PA9", "PA10", "PA11",
+                                               "PA12", "PA13", "PA14", "PA19",
+                                               "PA20", "PA25", "PA26", "PA27";
+                               allwinner,function = "gmac";
+                               /*
+                                * data lines in RGMII mode use DDR mode
+                                * and need a higher signal drive strength
+                                */
+                               allwinner,drive = <3>;
+                               allwinner,pull = <0>;
+                       };
                };
 
                ahb1_rst: reset@01c202c0 {
@@ -621,6 +692,23 @@
                        status = "disabled";
                };
 
+               gmac: ethernet@01c30000 {
+                       compatible = "allwinner,sun7i-a20-gmac";
+                       reg = <0x01c30000 0x1054>;
+                       interrupts = <0 82 4>;
+                       interrupt-names = "macirq";
+                       clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
+                       clock-names = "stmmaceth", "allwinner_gmac_tx";
+                       resets = <&ahb1_rst 17>;
+                       reset-names = "stmmaceth";
+                       snps,pbl = <2>;
+                       snps,fixed-burst;
+                       snps,force_sf_dma_mode;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
                timer@01c60000 {
                        compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
                        reg = <0x01c60000 0x1000>;