ARM: at91: move at91rm9200 sdramc defines to at91rm9200_sdramc.h

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-at91 / include / mach / at91rm9200_mc.h

diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
index d34e4ed89349639fc1c6bb5e3656da50c242006d..0eb031b7045117b90989007c1e92d3410d2d920d 100644 (file)
--- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
@@ -87,50 +87,6 @@
 #define                AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
 #define                        AT91_SMC_RWHOLD_(x)     ((x) << 28)
 
-/* SDRAM Controller registers */
-#define AT91_SDRAMC_MR         (AT91_MC + 0x90)        /* Mode Register */
-#define                AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
-#define                        AT91_SDRAMC_MODE_NORMAL         (0 << 0)
-#define                        AT91_SDRAMC_MODE_NOP            (1 << 0)
-#define                        AT91_SDRAMC_MODE_PRECHARGE      (2 << 0)
-#define                        AT91_SDRAMC_MODE_LMR            (3 << 0)
-#define                        AT91_SDRAMC_MODE_REFRESH        (4 << 0)
-#define                AT91_SDRAMC_DBW         (1   << 4)              /* Data Bus Width */
-#define                        AT91_SDRAMC_DBW_32      (0 << 4)
-#define                        AT91_SDRAMC_DBW_16      (1 << 4)
-
-#define AT91_SDRAMC_TR         (AT91_MC + 0x94)        /* Refresh Timer Register */
-#define                AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Count */
-
-#define AT91_SDRAMC_CR         (AT91_MC + 0x98)        /* Configuration Register */
-#define                AT91_SDRAMC_NC          (3   <<  0)             /* Number of Column Bits */
-#define                        AT91_SDRAMC_NC_8        (0 << 0)
-#define                        AT91_SDRAMC_NC_9        (1 << 0)
-#define                        AT91_SDRAMC_NC_10       (2 << 0)
-#define                        AT91_SDRAMC_NC_11       (3 << 0)
-#define                AT91_SDRAMC_NR          (3   <<  2)             /* Number of Row Bits */
-#define                        AT91_SDRAMC_NR_11       (0 << 2)
-#define                        AT91_SDRAMC_NR_12       (1 << 2)
-#define                        AT91_SDRAMC_NR_13       (2 << 2)
-#define                AT91_SDRAMC_NB          (1   <<  4)             /* Number of Banks */
-#define                        AT91_SDRAMC_NB_2        (0 << 4)
-#define                        AT91_SDRAMC_NB_4        (1 << 4)
-#define                AT91_SDRAMC_CAS         (3   <<  5)             /* CAS Latency */
-#define                        AT91_SDRAMC_CAS_2       (2 << 5)
-#define                AT91_SDRAMC_TWR         (0xf <<  7)             /* Write Recovery Delay */
-#define                AT91_SDRAMC_TRC         (0xf << 11)             /* Row Cycle Delay */
-#define                AT91_SDRAMC_TRP         (0xf << 15)             /* Row Precharge Delay */
-#define                AT91_SDRAMC_TRCD        (0xf << 19)             /* Row to Column Delay */
-#define                AT91_SDRAMC_TRAS        (0xf << 23)             /* Active to Precharge Delay */
-#define                AT91_SDRAMC_TXSR        (0xf << 27)             /* Exit Self Refresh to Active Delay */
-
-#define AT91_SDRAMC_SRR                (AT91_MC + 0x9c)        /* Self Refresh Register */
-#define AT91_SDRAMC_LPR                (AT91_MC + 0xa0)        /* Low Power Register */
-#define AT91_SDRAMC_IER                (AT91_MC + 0xa4)        /* Interrupt Enable Register */
-#define AT91_SDRAMC_IDR                (AT91_MC + 0xa8)        /* Interrupt Disable Register */
-#define AT91_SDRAMC_IMR                (AT91_MC + 0xac)        /* Interrupt Mask Register */
-#define AT91_SDRAMC_ISR                (AT91_MC + 0xb0)        /* Interrupt Status Register */
-
 /* Burst Flash Controller register */
 #define AT91_BFC_MR            (AT91_MC + 0xc0)        /* Mode Register */
 #define                AT91_BFC_BFCOM          (3   <<  0)             /* Burst Flash Controller Operating Mode */