Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-at91 / pm.h

diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 86c0aa819d2590aae5af7146e5e3a4ebeb086e35..ecd875a91d5218281049b6b4b36924ddcc62b1d3 100644 (file)
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -15,100 +15,16 @@
 
 #include <mach/at91_ramc.h>
 
-#ifdef CONFIG_PM
-extern void at91_pm_set_standby(void (*at91_standby)(void));
-#else
-static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
-#endif
-
-/*
- * The AT91RM9200 goes into self-refresh mode with this command, and will
- * terminate self-refresh automatically on the next SDRAM access.
- *
- * Self-refresh mode is exited as soon as a memory access is made, but we don't
- * know for sure when that happens. However, we need to restore the low-power
- * mode if it was enabled before going idle. Restoring low-power mode while
- * still in self-refresh is "not recommended", but seems to work.
- */
-
-static inline void at91rm9200_standby(void)
-{
-       u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
-
-       asm volatile(
-               "b    1f\n\t"
-               ".align    5\n\t"
-               "1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
-               "    str    %0, [%1, %2]\n\t"
-               "    str    %3, [%1, %4]\n\t"
-               "    mcr    p15, 0, %0, c7, c0, 4\n\t"
-               "    str    %5, [%1, %2]"
-               :
-               : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
-                 "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
-                 "r" (lpr));
-}
-
-/* We manage both DDRAM/SDRAM controllers, we need more than one value to
- * remember.
- */
-static inline void at91_ddr_standby(void)
-{
-       /* Those two values allow us to delay self-refresh activation
-        * to the maximum. */
-       u32 lpr0, lpr1 = 0;
-       u32 saved_lpr0, saved_lpr1 = 0;
-
-       if (at91_ramc_base[1]) {
-               saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
-               lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
-               lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
-       }
-
-       saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
-       lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
-       lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
-
-       /* self-refresh mode now */
-       at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
-       if (at91_ramc_base[1])
-               at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
-
-       cpu_do_idle();
-
-       at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
-       if (at91_ramc_base[1])
-               at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
-}
-
-/* We manage both DDRAM/SDRAM controllers, we need more than one value to
- * remember.
- */
-static inline void at91sam9_sdram_standby(void)
-{
-       u32 lpr0, lpr1 = 0;
-       u32 saved_lpr0, saved_lpr1 = 0;
-
-       if (at91_ramc_base[1]) {
-               saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
-               lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
-               lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
-       }
-
-       saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
-       lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
-       lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
+#define AT91_MEMCTRL_MC                0
+#define AT91_MEMCTRL_SDRAMC    1
+#define AT91_MEMCTRL_DDRSDR    2
 
-       /* self-refresh mode now */
-       at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
-       if (at91_ramc_base[1])
-               at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
+#define        AT91_PM_MEMTYPE_MASK    0x0f
 
-       cpu_do_idle();
+#define        AT91_PM_MODE_OFFSET     4
+#define        AT91_PM_MODE_MASK       0x01
+#define        AT91_PM_MODE(x)         (((x) & AT91_PM_MODE_MASK) << AT91_PM_MODE_OFFSET)
 
-       at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
-       if (at91_ramc_base[1])
-               at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
-}
+#define        AT91_PM_SLOW_CLOCK      0x01
 
 #endif