Merge branch 'next/dt2' into HEAD

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-exynos / clock-exynos5.c

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 17e6c77231fa0dbbd6c3ca4d0c16ddfcae335f3f..c44ca1ee1b8d0196de2ac413bad5af226bc83bc9 100644 (file)
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -166,11 +166,6 @@ static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
 }
 
-static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
-{
-       return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
-}
-
 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 {
        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
@@ -552,6 +547,68 @@ static struct clksrc_clk exynos5_clk_aclk_66 = {
        .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
 };
 
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
+       .clk    = {
+               .name           = "mout_aclk_300_gscl_mid",
+       },
+       .sources = &exynos5_clkset_aclk,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
+       [0] = &exynos5_clk_sclk_vpll.clk,
+       [1] = &exynos5_clk_mout_cpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
+       .sources        = exynos5_clkset_aclk_300_mid1_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
+       .clk    = {
+               .name           = "mout_aclk_300_gscl_mid1",
+       },
+       .sources = &exynos5_clkset_aclk_300_gscl_mid1,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
+       [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
+       [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
+       .sources        = exynos5_clkset_aclk_300_gscl_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
+       .clk    = {
+               .name           = "mout_aclk_300_gscl",
+       },
+       .sources = &exynos5_clkset_aclk_300_gscl,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_gscl_300_list[] = {
+       [0] = &clk_ext_xtal_mux,
+       [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_gscl_300 = {
+       .sources        = exynos5_clk_src_gscl_300_list,
+       .nr_sources     = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
+       .clk    = {
+               .name           = "aclk_300_gscl",
+       },
+       .sources = &exynos5_clk_src_gscl_300,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
+};
+
 static struct clk exynos5_init_clocks_off[] = {
        {
                .name           = "timers",
@@ -666,10 +723,6 @@ static struct clk exynos5_init_clocks_off[] = {
                .name           = "usbotg",
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 7),
-       }, {
-               .name           = "gps",
-               .enable         = exynos5_clk_ip_gps_ctrl,
-               .ctrlbit        = ((1 << 3) | (1 << 2) | (1 << 0)),
        }, {
                .name           = "nfcon",
                .enable         = exynos5_clk_ip_fsys_ctrl,
@@ -758,6 +811,26 @@ static struct clk exynos5_init_clocks_off[] = {
                .parent         = &exynos5_clk_aclk_66.clk,
                .enable         = exynos5_clk_ip_peric_ctrl,
                .ctrlbit        = (1 << 18),
+       }, {
+               .name           = "gscl",
+               .devname        = "exynos-gsc.0",
+               .enable         = exynos5_clk_ip_gscl_ctrl,
+               .ctrlbit        = (1 << 0),
+       }, {
+               .name           = "gscl",
+               .devname        = "exynos-gsc.1",
+               .enable         = exynos5_clk_ip_gscl_ctrl,
+               .ctrlbit        = (1 << 1),
+       }, {
+               .name           = "gscl",
+               .devname        = "exynos-gsc.2",
+               .enable         = exynos5_clk_ip_gscl_ctrl,
+               .ctrlbit        = (1 << 2),
+       }, {
+               .name           = "gscl",
+               .devname        = "exynos-gsc.3",
+               .enable         = exynos5_clk_ip_gscl_ctrl,
+               .ctrlbit        = (1 << 3),
        }, {
                .name           = SYSMMU_CLOCK_NAME,
                .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
@@ -886,6 +959,13 @@ static struct clk exynos5_clk_mdma1 = {
        .ctrlbit        = (1 << 4),
 };
 
+static struct clk exynos5_clk_fimd1 = {
+       .name           = "fimd",
+       .devname        = "exynos5-fb.1",
+       .enable         = exynos5_clk_ip_disp1_ctrl,
+       .ctrlbit        = (1 << 0),
+};
+
 struct clk *exynos5_clkset_group_list[] = {
        [0] = &clk_ext_xtal_mux,
        [1] = NULL,
@@ -1115,18 +1195,20 @@ static struct clksrc_clk exynos5_clk_sclk_spi2 = {
        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
 };
 
+struct clksrc_clk exynos5_clk_sclk_fimd1 = {
+       .clk    = {
+               .name           = "sclk_fimd",
+               .devname        = "exynos5-fb.1",
+               .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
+               .ctrlbit        = (1 << 0),
+       },
+       .sources = &exynos5_clkset_group,
+       .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+       .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+};
+
 static struct clksrc_clk exynos5_clksrcs[] = {
        {
-               .clk    = {
-                       .name           = "sclk_fimd",
-                       .devname        = "s3cfb.1",
-                       .enable         = exynos5_clksrc_mask_disp1_0_ctrl,
-                       .ctrlbit        = (1 << 0),
-               },
-               .sources = &exynos5_clkset_group,
-               .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
-               .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
-       }, {
                .clk    = {
                        .name           = "aclk_266_gscl",
                },
@@ -1212,6 +1294,10 @@ static struct clksrc_clk *exynos5_sysclks[] = {
        &exynos5_clk_aclk_266,
        &exynos5_clk_aclk_200,
        &exynos5_clk_aclk_166,
+       &exynos5_clk_aclk_300_gscl,
+       &exynos5_clk_mout_aclk_300_gscl,
+       &exynos5_clk_mout_aclk_300_gscl_mid,
+       &exynos5_clk_mout_aclk_300_gscl_mid1,
        &exynos5_clk_aclk_66_pre,
        &exynos5_clk_aclk_66,
        &exynos5_clk_dout_mmc0,
@@ -1227,12 +1313,14 @@ static struct clksrc_clk *exynos5_sysclks[] = {
        &exynos5_clk_mdout_spi0,
        &exynos5_clk_mdout_spi1,
        &exynos5_clk_mdout_spi2,
+       &exynos5_clk_sclk_fimd1,
 };
 
 static struct clk *exynos5_clk_cdev[] = {
        &exynos5_clk_pdma0,
        &exynos5_clk_pdma1,
        &exynos5_clk_mdma1,
+       &exynos5_clk_fimd1,
 };
 
 static struct clksrc_clk *exynos5_clksrc_cdev[] = {
@@ -1261,6 +1349,7 @@ static struct clk_lookup exynos5_clk_lookup[] = {
        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+       CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
 };
 
 static unsigned long exynos5_epll_get_rate(struct clk *clk)