Merge tag 'modules-next-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-exynos / clock-exynos5.c

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 4478757b930126bc112062a9956ab5c43124e97d..e9d7b80bae492cf241818d989e3f926d9577761e 100644 (file)
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -80,6 +80,8 @@ static struct sleep_save exynos5_clock_save[] = {
        SAVE_ITEM(EXYNOS5_VPLL_CON0),
        SAVE_ITEM(EXYNOS5_VPLL_CON1),
        SAVE_ITEM(EXYNOS5_VPLL_CON2),
+       SAVE_ITEM(EXYNOS5_PWR_CTRL1),
+       SAVE_ITEM(EXYNOS5_PWR_CTRL2),
 };
 #endif
 
@@ -196,6 +198,11 @@ static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
 }
 
+static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+       return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
 /* Core list of CMU_CPU side */
 
 static struct clksrc_clk exynos5_clk_mout_apll = {
@@ -615,6 +622,11 @@ static struct clk exynos5_init_clocks_off[] = {
                .parent         = &exynos5_clk_aclk_66.clk,
                .enable         = exynos5_clk_ip_peric_ctrl,
                .ctrlbit        = (1 << 24),
+       }, {
+               .name           = "tmu_apbif",
+               .parent         = &exynos5_clk_aclk_66.clk,
+               .enable         = exynos5_clk_ip_peris_ctrl,
+               .ctrlbit        = (1 << 21),
        }, {
                .name           = "rtc",
                .parent         = &exynos5_clk_aclk_66.clk,
@@ -651,32 +663,47 @@ static struct clk exynos5_init_clocks_off[] = {
                .ctrlbit        = (1 << 15),
        }, {
                .name           = "sata",
-               .devname        = "ahci",
+               .devname        = "exynos5-sata",
+               .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 6),
        }, {
-               .name           = "sata_phy",
+               .name           = "sata-phy",
+               .devname        = "exynos5-sata-phy",
+               .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 24),
        }, {
-               .name           = "sata_phy_i2c",
+               .name           = "i2c",
+               .devname        = "exynos5-sata-phy-i2c",
+               .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 25),
        }, {
                .name           = "mfc",
-               .devname        = "s5p-mfc",
+               .devname        = "s5p-mfc-v6",
                .enable         = exynos5_clk_ip_mfc_ctrl,
                .ctrlbit        = (1 << 0),
        }, {
                .name           = "hdmi",
-               .devname        = "exynos4-hdmi",
+               .devname        = "exynos5-hdmi",
                .enable         = exynos5_clk_ip_disp1_ctrl,
                .ctrlbit        = (1 << 6),
+       }, {
+               .name           = "hdmiphy",
+               .devname        = "exynos5-hdmi",
+               .enable         = exynos5_clk_hdmiphy_ctrl,
+               .ctrlbit        = (1 << 0),
        }, {
                .name           = "mixer",
-               .devname        = "s5p-mixer",
+               .devname        = "exynos5-mixer",
                .enable         = exynos5_clk_ip_disp1_ctrl,
                .ctrlbit        = (1 << 5),
+       }, {
+               .name           = "dp",
+               .devname        = "exynos-dp",
+               .enable         = exynos5_clk_ip_disp1_ctrl,
+               .ctrlbit        = (1 << 4),
        }, {
                .name           = "jpeg",
                .enable         = exynos5_clk_ip_gen_ctrl,
@@ -1224,6 +1251,16 @@ static struct clksrc_clk exynos5_clksrcs[] = {
                .sources = &exynos5_clkset_aclk,
                .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
                .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+       }, {
+               .clk    = {
+                       .name           = "sclk_sata",
+                       .devname        = "exynos5-sata",
+                       .enable         = exynos5_clksrc_mask_fsys_ctrl,
+                       .ctrlbit        = (1 << 24),
+               },
+               .sources = &exynos5_clkset_aclk,
+               .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
+               .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
        }, {
                .clk    = {
                        .name           = "sclk_gscl_wrap",