Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-exynos / include / mach / irqs.h

diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 591e78521a9f11f6de5114c8f717933efe4c9fd7..7a4b4789eb7288205fcfcd555dcf50ffdb962753 100644 (file)
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -154,6 +154,13 @@
 #define EXYNOS4_IRQ_SYSMMU_MFC_M1_0    COMBINER_IRQ(5, 6)
 #define EXYNOS4_IRQ_SYSMMU_PCIE_0      COMBINER_IRQ(5, 7)
 
+#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0        COMBINER_IRQ(16, 0)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0        COMBINER_IRQ(16, 1)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0  COMBINER_IRQ(16, 2)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0  COMBINER_IRQ(16, 3)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0   COMBINER_IRQ(16, 4)
+#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0   COMBINER_IRQ(16, 5)
+
 #define EXYNOS4_IRQ_FIMD0_FIFO         COMBINER_IRQ(11, 0)
 #define EXYNOS4_IRQ_FIMD0_VSYNC                COMBINER_IRQ(11, 1)
 #define EXYNOS4_IRQ_FIMD0_SYSTEM       COMBINER_IRQ(11, 2)
@@ -189,6 +196,7 @@
 #define IRQ_IIC7                       EXYNOS4_IRQ_IIC7
 
 #define IRQ_USB_HOST                   EXYNOS4_IRQ_USB_HOST
+#define IRQ_OTG                                EXYNOS4_IRQ_USB_HSOTG
 
 #define IRQ_HSMMC0                     EXYNOS4_IRQ_HSMMC0
 #define IRQ_HSMMC1                     EXYNOS4_IRQ_HSMMC1
@@ -220,24 +228,6 @@
 #define IRQ_KEYPAD                     EXYNOS4_IRQ_KEYPAD
 #define IRQ_PMU                                EXYNOS4_IRQ_PMU
 
-#define IRQ_SYSMMU_MDMA0_0             EXYNOS4_IRQ_SYSMMU_MDMA0_0
-#define IRQ_SYSMMU_SSS_0                EXYNOS4_IRQ_SYSMMU_SSS_0
-#define IRQ_SYSMMU_FIMC0_0              EXYNOS4_IRQ_SYSMMU_FIMC0_0
-#define IRQ_SYSMMU_FIMC1_0              EXYNOS4_IRQ_SYSMMU_FIMC1_0
-#define IRQ_SYSMMU_FIMC2_0              EXYNOS4_IRQ_SYSMMU_FIMC2_0
-#define IRQ_SYSMMU_FIMC3_0              EXYNOS4_IRQ_SYSMMU_FIMC3_0
-#define IRQ_SYSMMU_JPEG_0               EXYNOS4_IRQ_SYSMMU_JPEG_0
-#define IRQ_SYSMMU_2D_0                 EXYNOS4_IRQ_SYSMMU_2D_0
-
-#define IRQ_SYSMMU_ROTATOR_0            EXYNOS4_IRQ_SYSMMU_ROTATOR_0
-#define IRQ_SYSMMU_MDMA1_0              EXYNOS4_IRQ_SYSMMU_MDMA1_0
-#define IRQ_SYSMMU_LCD0_M0_0            EXYNOS4_IRQ_SYSMMU_LCD0_M0_0
-#define IRQ_SYSMMU_LCD1_M1_0            EXYNOS4_IRQ_SYSMMU_LCD1_M1_0
-#define IRQ_SYSMMU_TV_M0_0              EXYNOS4_IRQ_SYSMMU_TV_M0_0
-#define IRQ_SYSMMU_MFC_M0_0             EXYNOS4_IRQ_SYSMMU_MFC_M0_0
-#define IRQ_SYSMMU_MFC_M1_0             EXYNOS4_IRQ_SYSMMU_MFC_M1_0
-#define IRQ_SYSMMU_PCIE_0               EXYNOS4_IRQ_SYSMMU_PCIE_0
-
 #define IRQ_FIMD0_FIFO                 EXYNOS4_IRQ_FIMD0_FIFO
 #define IRQ_FIMD0_VSYNC                        EXYNOS4_IRQ_FIMD0_VSYNC
 #define IRQ_FIMD0_SYSTEM               EXYNOS4_IRQ_FIMD0_SYSTEM
@@ -297,6 +287,7 @@
 #define EXYNOS5_IRQ_MIPICSI1           IRQ_SPI(80)
 #define EXYNOS5_IRQ_EFNFCON_DMA_ABORT  IRQ_SPI(81)
 #define EXYNOS5_IRQ_MIPIDSI0           IRQ_SPI(82)
+#define EXYNOS5_IRQ_WDT_IOP            IRQ_SPI(83)
 #define EXYNOS5_IRQ_ROTATOR            IRQ_SPI(84)
 #define EXYNOS5_IRQ_GSC0               IRQ_SPI(85)
 #define EXYNOS5_IRQ_GSC1               IRQ_SPI(86)
@@ -305,8 +296,8 @@
 #define EXYNOS5_IRQ_JPEG               IRQ_SPI(89)
 #define EXYNOS5_IRQ_EFNFCON_DMA                IRQ_SPI(90)
 #define EXYNOS5_IRQ_2D                 IRQ_SPI(91)
-#define EXYNOS5_IRQ_SFMC0              IRQ_SPI(92)
-#define EXYNOS5_IRQ_SFMC1              IRQ_SPI(93)
+#define EXYNOS5_IRQ_EFNFCON_0          IRQ_SPI(92)
+#define EXYNOS5_IRQ_EFNFCON_1          IRQ_SPI(93)
 #define EXYNOS5_IRQ_MIXER              IRQ_SPI(94)
 #define EXYNOS5_IRQ_HDMI               IRQ_SPI(95)
 #define EXYNOS5_IRQ_MFC                        IRQ_SPI(96)
@@ -320,7 +311,7 @@
 #define EXYNOS5_IRQ_PCM2               IRQ_SPI(104)
 #define EXYNOS5_IRQ_SPDIF              IRQ_SPI(105)
 #define EXYNOS5_IRQ_ADC0               IRQ_SPI(106)
-
+#define EXYNOS5_IRQ_ADC1               IRQ_SPI(107)
 #define EXYNOS5_IRQ_SATA_PHY           IRQ_SPI(108)
 #define EXYNOS5_IRQ_SATA_PMEMREQ       IRQ_SPI(109)
 #define EXYNOS5_IRQ_CAM_C              IRQ_SPI(110)
@@ -329,8 +320,9 @@
 #define EXYNOS5_IRQ_DP1_INTP1          IRQ_SPI(113)
 #define EXYNOS5_IRQ_CEC                        IRQ_SPI(114)
 #define EXYNOS5_IRQ_SATA               IRQ_SPI(115)
-#define EXYNOS5_IRQ_NFCON              IRQ_SPI(116)
 
+#define EXYNOS5_IRQ_MCT_L0             IRQ_SPI(120)
+#define EXYNOS5_IRQ_MCT_L1             IRQ_SPI(121)
 #define EXYNOS5_IRQ_MMC44              IRQ_SPI(123)
 #define EXYNOS5_IRQ_MDMA1              IRQ_SPI(124)
 #define EXYNOS5_IRQ_FIMC_LITE0         IRQ_SPI(125)
@@ -338,7 +330,6 @@
 #define EXYNOS5_IRQ_RP_TIMER           IRQ_SPI(127)
 
 #define EXYNOS5_IRQ_PMU                        COMBINER_IRQ(1, 2)
-#define EXYNOS5_IRQ_PMU_CPU1           COMBINER_IRQ(1, 6)
 
 #define EXYNOS5_IRQ_SYSMMU_GSC0_0      COMBINER_IRQ(2, 0)
 #define EXYNOS5_IRQ_SYSMMU_GSC0_1      COMBINER_IRQ(2, 1)
@@ -349,6 +340,8 @@
 #define EXYNOS5_IRQ_SYSMMU_GSC3_0      COMBINER_IRQ(2, 6)
 #define EXYNOS5_IRQ_SYSMMU_GSC3_1      COMBINER_IRQ(2, 7)
 
+#define EXYNOS5_IRQ_SYSMMU_LITE2_0     COMBINER_IRQ(3, 0)
+#define EXYNOS5_IRQ_SYSMMU_LITE2_1     COMBINER_IRQ(3, 1)
 #define EXYNOS5_IRQ_SYSMMU_FIMD1_0     COMBINER_IRQ(3, 2)
 #define EXYNOS5_IRQ_SYSMMU_FIMD1_1     COMBINER_IRQ(3, 3)
 #define EXYNOS5_IRQ_SYSMMU_LITE0_0     COMBINER_IRQ(3, 4)
@@ -372,8 +365,8 @@
 
 #define EXYNOS5_IRQ_SYSMMU_ARM_0       COMBINER_IRQ(6, 0)
 #define EXYNOS5_IRQ_SYSMMU_ARM_1       COMBINER_IRQ(6, 1)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_0     COMBINER_IRQ(6, 2)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_1     COMBINER_IRQ(6, 3)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_0     COMBINER_IRQ(6, 2)
+#define EXYNOS5_IRQ_SYSMMU_MFC_R_1     COMBINER_IRQ(6, 3)
 #define EXYNOS5_IRQ_SYSMMU_RTIC_0      COMBINER_IRQ(6, 4)
 #define EXYNOS5_IRQ_SYSMMU_RTIC_1      COMBINER_IRQ(6, 5)
 #define EXYNOS5_IRQ_SYSMMU_SSS_0       COMBINER_IRQ(6, 6)
@@ -385,11 +378,9 @@
 #define EXYNOS5_IRQ_SYSMMU_MDMA1_1     COMBINER_IRQ(7, 3)
 #define EXYNOS5_IRQ_SYSMMU_TV_0                COMBINER_IRQ(7, 4)
 #define EXYNOS5_IRQ_SYSMMU_TV_1                COMBINER_IRQ(7, 5)
-#define EXYNOS5_IRQ_SYSMMU_GPSX_0      COMBINER_IRQ(7, 6)
-#define EXYNOS5_IRQ_SYSMMU_GPSX_1      COMBINER_IRQ(7, 7)
 
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_0     COMBINER_IRQ(8, 5)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_1     COMBINER_IRQ(8, 6)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_0     COMBINER_IRQ(8, 5)
+#define EXYNOS5_IRQ_SYSMMU_MFC_L_1     COMBINER_IRQ(8, 6)
 
 #define EXYNOS5_IRQ_SYSMMU_DIS1_0      COMBINER_IRQ(9, 4)
 #define EXYNOS5_IRQ_SYSMMU_DIS1_1      COMBINER_IRQ(9, 5)
@@ -405,17 +396,24 @@
 #define EXYNOS5_IRQ_SYSMMU_DRC_0       COMBINER_IRQ(11, 6)
 #define EXYNOS5_IRQ_SYSMMU_DRC_1       COMBINER_IRQ(11, 7)
 
+#define EXYNOS5_IRQ_MDMA1_ABORT                COMBINER_IRQ(13, 1)
+
+#define EXYNOS5_IRQ_MDMA0_ABORT                COMBINER_IRQ(15, 3)
+
 #define EXYNOS5_IRQ_FIMD1_FIFO         COMBINER_IRQ(18, 4)
 #define EXYNOS5_IRQ_FIMD1_VSYNC                COMBINER_IRQ(18, 5)
 #define EXYNOS5_IRQ_FIMD1_SYSTEM       COMBINER_IRQ(18, 6)
 
+#define EXYNOS5_IRQ_ARMIOP_GIC         COMBINER_IRQ(19, 0)
+#define EXYNOS5_IRQ_ARMISP_GIC         COMBINER_IRQ(19, 1)
+#define EXYNOS5_IRQ_IOP_GIC            COMBINER_IRQ(19, 3)
+#define EXYNOS5_IRQ_ISP_GIC            COMBINER_IRQ(19, 4)
+
+#define EXYNOS5_IRQ_PMU_CPU1           COMBINER_IRQ(22, 4)
+
 #define EXYNOS5_IRQ_EINT0              COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_L0             COMBINER_IRQ(23, 1)
-#define EXYNOS5_IRQ_MCT_L1             COMBINER_IRQ(23, 2)
 #define EXYNOS5_IRQ_MCT_G0             COMBINER_IRQ(23, 3)
 #define EXYNOS5_IRQ_MCT_G1             COMBINER_IRQ(23, 4)
-#define EXYNOS5_IRQ_MCT_G2             COMBINER_IRQ(23, 5)
-#define EXYNOS5_IRQ_MCT_G3             COMBINER_IRQ(23, 6)
 
 #define EXYNOS5_IRQ_EINT1              COMBINER_IRQ(24, 0)
 #define EXYNOS5_IRQ_SYSMMU_LITE1_0     COMBINER_IRQ(24, 1)
@@ -446,7 +444,7 @@
 
 #define EXYNOS5_MAX_COMBINER_NR                32
 
-#define EXYNOS5_IRQ_GPIO1_NR_GROUPS    13
+#define EXYNOS5_IRQ_GPIO1_NR_GROUPS    14
 #define EXYNOS5_IRQ_GPIO2_NR_GROUPS    9
 #define EXYNOS5_IRQ_GPIO3_NR_GROUPS    5
 #define EXYNOS5_IRQ_GPIO4_NR_GROUPS    1