ARM: meson: add basic support for MesonX SoCs

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-mvebu / platsmp-a9.c

diff --git a/arch/arm/mach-mvebu/platsmp-a9.c b/arch/arm/mach-mvebu/platsmp-a9.c
index 96c2c59e34b67bc108d05f8f81c1255faa9f9174..47a71a924b965f130b6e21a667eaaa5d7adb53d5 100644 (file)
--- a/arch/arm/mach-mvebu/platsmp-a9.c
+++ b/arch/arm/mach-mvebu/platsmp-a9.c
@@ -20,33 +20,8 @@
 #include <asm/smp_scu.h>
 #include <asm/smp_plat.h>
 #include "common.h"
-#include "mvebu-soc-id.h"
 #include "pmsu.h"
 
-#define CRYPT0_ENG_ID   41
-#define CRYPT0_ENG_ATTR 0x1
-#define SRAM_PHYS_BASE  0xFFFF0000
-
-#define BOOTROM_BASE    0xFFF00000
-#define BOOTROM_SIZE    0x100000
-
-extern unsigned char armada_375_smp_cpu1_enable_code_end;
-extern unsigned char armada_375_smp_cpu1_enable_code_start;
-
-void armada_375_smp_cpu1_enable_wa(void)
-{
-       void __iomem *sram_virt_base;
-
-       mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
-       mvebu_mbus_add_window_by_id(CRYPT0_ENG_ID, CRYPT0_ENG_ATTR,
-                               SRAM_PHYS_BASE, SZ_64K);
-       sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
-
-       memcpy(sram_virt_base, &armada_375_smp_cpu1_enable_code_start,
-              &armada_375_smp_cpu1_enable_code_end
-              - &armada_375_smp_cpu1_enable_code_start);
-}
-
 extern void mvebu_cortex_a9_secondary_startup(void);
 
 static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
@@ -63,21 +38,10 @@ static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
         * address.
         */
        hw_cpu = cpu_logical_map(cpu);
-
-       if (of_machine_is_compatible("marvell,armada375")) {
-               u32 dev, rev;
-
-               if (mvebu_get_soc_id(&dev, &rev) == 0 &&
-                   rev == ARMADA_375_Z1_REV)
-                       armada_375_smp_cpu1_enable_wa();
-
+       if (of_machine_is_compatible("marvell,armada375"))
                mvebu_system_controller_set_cpu_boot_addr(mvebu_cortex_a9_secondary_startup);
-       }
-       else {
-               mvebu_pmsu_set_cpu_boot_addr(hw_cpu,
-                                            mvebu_cortex_a9_secondary_startup);
-       }
-
+       else
+               mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cortex_a9_secondary_startup);
        smp_wmb();
        ret = mvebu_cpu_reset_deassert(hw_cpu);
        if (ret) {
@@ -91,9 +55,6 @@ static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
 
 static struct smp_operations mvebu_cortex_a9_smp_ops __initdata = {
        .smp_boot_secondary     = mvebu_cortex_a9_boot_secondary,
-#ifdef CONFIG_HOTPLUG_CPU
-       .cpu_die                = armada_xp_cpu_die,
-#endif
 };
 
 CPU_METHOD_OF_DECLARE(mvebu_armada_375_smp, "marvell,armada-375-smp",