Merge branch 'cgroup-rmdir-updates' into cgroup/for-3.8

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-omap2 / clkt34xx_dpll3m2.c

diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index 298887b5bf66c5168a248372b26d5410658f1ae4..7c6da2f731dc75683512af15df6510886f03c1e8 100644 (file)
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
        struct omap_sdrc_params *sdrc_cs0;
        struct omap_sdrc_params *sdrc_cs1;
        int ret;
+       unsigned long clkrate;
 
        if (!clk || !rate)
                return -EINVAL;
@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
        if (validrate != rate)
                return -EINVAL;
 
-       sdrcrate = sdrc_ick_p->rate;
-       if (rate > clk->rate)
-               sdrcrate <<= ((rate / clk->rate) >> 1);
+       sdrcrate = __clk_get_rate(sdrc_ick_p);
+       clkrate = __clk_get_rate(clk);
+       if (rate > clkrate)
+               sdrcrate <<= ((rate / clkrate) >> 1);
        else
-               sdrcrate >>= ((clk->rate / rate) >> 1);
+               sdrcrate >>= ((clkrate / rate) >> 1);
 
        ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
        if (ret)
@@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
        /*
         * XXX This only needs to be done when the CPU frequency changes
         */
-       _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+       _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
        c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
        c += 1;  /* for safety */
        c *= SDRC_MPURATE_LOOPS;
@@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
        if (c == 0)
                c = 1;
 
-       pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
-                validrate);
+       pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
+                clkrate, validrate);
        pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
                 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
@@ -102,14 +104,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
        if (sdrc_cs1)
                omap3_configure_core_dpll(
-                                 new_div, unlock_dll, c, rate > clk->rate,
+                                 new_div, unlock_dll, c, rate > clkrate,
                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                                  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
                                  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
        else
                omap3_configure_core_dpll(
-                                 new_div, unlock_dll, c, rate > clk->rate,
+                                 new_div, unlock_dll, c, rate > clkrate,
                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                                  0, 0, 0, 0);