Merge branch 'cgroup-rmdir-updates' into cgroup/for-3.8

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-omap2 / clkt_dpll.c

diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 83b658bf385ae4b01c8ea279313016fa991f91d2..80411142f4823c9626115fb5847f87f35d7f1d8c 100644 (file)
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
        dd = clk->dpll_data;
 
        /* DPLL divider must result in a valid jitter correction val */
-       fint = clk->parent->rate / n;
+       fint = __clk_get_rate(__clk_get_parent(clk)) / n;
 
        if (cpu_is_omap24xx()) {
                /* Should not be called for OMAP2, so warn if it is called */
@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
        if (cpu_is_omap24xx()) {
                if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                       return dd->clk_bypass->rate;
+                       return __clk_get_rate(dd->clk_bypass);
        } else if (cpu_is_omap34xx()) {
                if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP3XXX_EN_DPLL_FRBYPASS)
-                       return dd->clk_bypass->rate;
+                       return __clk_get_rate(dd->clk_bypass);
        } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
                if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
                    v == OMAP4XXX_EN_DPLL_FRBYPASS ||
                    v == OMAP4XXX_EN_DPLL_MNBYPASS)
-                       return dd->clk_bypass->rate;
+                       return __clk_get_rate(dd->clk_bypass);
        }
 
        v = __raw_readl(dd->mult_div1_reg);
@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
        dpll_div = v & dd->div1_mask;
        dpll_div >>= __ffs(dd->div1_mask);
 
-       dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
+       dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
        do_div(dpll_clk, dpll_div + 1);
 
        return dpll_clk;
@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
        unsigned long scaled_rt_rp;
        unsigned long new_rate = 0;
        struct dpll_data *dd;
+       unsigned long ref_rate;
+       const char *clk_name;
 
        if (!clk || !clk->dpll_data)
                return ~0;
 
        dd = clk->dpll_data;
 
+       ref_rate = __clk_get_rate(dd->clk_ref);
+       clk_name = __clk_get_name(clk);
        pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
-                clk->name, target_rate);
+                clk_name, target_rate);
 
-       scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+       scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
        scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
 
        dd->last_rounded_rate = 0;
@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
                        break;
 
                r = _dpll_test_mult(&m, n, &new_rate, target_rate,
-                                   dd->clk_ref->rate);
+                                   ref_rate);
 
                /* m can't be set low enough for this n - try with a larger n */
                if (r == DPLL_MULT_UNDERFLOW)
                        continue;
 
                pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
-                        clk->name, m, n, new_rate);
+                        clk_name, m, n, new_rate);
 
                if (target_rate == new_rate) {
                        dd->last_rounded_m = m;
@@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
        }
 
        if (target_rate != new_rate) {
-               pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
-                        target_rate);
+               pr_debug("clock: %s: cannot round to rate %ld\n",
+                        clk_name, target_rate);
                return ~0;
        }