RealView: Move the SCU initialisation out of __v6_setup

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-realview / platsmp.c

diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index b8484e15dacb7f3e8f3d69ca09ea58334ea47b42..2ff1acaf2be71757559c629b906a0b6f7aa99e67 100644 (file)
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -15,9 +15,12 @@
 #include <linux/smp.h>
 
 #include <asm/cacheflush.h>
-#include <asm/hardware/arm_scu.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
+#include <asm/mach-types.h>
+
+#include <asm/arch/board-eb.h>
+#include <asm/arch/scu.h>
 
 extern void realview_secondary_startup(void);
 
@@ -30,10 +33,36 @@ volatile int __cpuinitdata pen_release = -1;
 static unsigned int __init get_core_count(void)
 {
        unsigned int ncores;
+       void __iomem *scu_base = 0;
+
+       if (machine_is_realview_eb() && core_tile_eb11mp())
+               scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
+
+       if (scu_base) {
+               ncores = __raw_readl(scu_base + SCU_CONFIG);
+               ncores = (ncores & 0x03) + 1;
+       } else
+               ncores = 1;
+
+       return ncores;
+}
 
-       ncores = __raw_readl(__io_address(REALVIEW_MPCORE_SCU_BASE) + SCU_CONFIG);
+/*
+ * Setup the SCU
+ */
+static void scu_enable(void)
+{
+       u32 scu_ctrl;
+       void __iomem *scu_base;
 
-       return (ncores & 0x03) + 1;
+       if (machine_is_realview_eb() && core_tile_eb11mp())
+               scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
+       else
+               BUG();
+
+       scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
+       scu_ctrl |= 1;
+       __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
 }
 
 static DEFINE_SPINLOCK(boot_lock);
@@ -52,13 +81,14 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         * core (e.g. timer irq), then they will not have been enabled
         * for us: do so
         */
-       gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE));
+       gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
 
        /*
         * let the primary processor know we're out of the
         * pen, then head off into the C entry point
         */
        pen_release = -1;
+       smp_wmb();
 
        /*
         * Synchronise with the boot thread.
@@ -102,6 +132,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 
        timeout = jiffies + (1 * HZ);
        while (time_before(jiffies, timeout)) {
+               smp_rmb();
                if (pen_release == -1)
                        break;
 
@@ -185,10 +216,15 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
        if (max_cpus > ncores)
                max_cpus = ncores;
 
+#ifdef CONFIG_LOCAL_TIMERS
        /*
-        * Enable the local timer for primary CPU
+        * Enable the local timer for primary CPU. If the device is
+        * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
+        * realview_timer_init
         */
-       local_timer_setup(cpu);
+       if (machine_is_realview_eb() && core_tile_eb11mp())
+               local_timer_setup(cpu);
+#endif
 
        /*
         * Initialise the present map, which describes the set of CPUs
@@ -198,11 +234,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                cpu_set(i, cpu_present_map);
 
        /*
-        * Do we need any more CPUs? If so, then let them know where
-        * to start. Note that, on modern versions of MILO, the "poke"
-        * doesn't actually do anything until each individual core is
-        * sent a soft interrupt to get it out of WFI
+        * Initialise the SCU if there are more than one CPU and let
+        * them know where to start. Note that, on modern versions of
+        * MILO, the "poke" doesn't actually do anything until each
+        * individual core is sent a soft interrupt to get it out of
+        * WFI
         */
-       if (max_cpus > 1)
+       if (max_cpus > 1) {
+               scu_enable();
                poke_milo();
+       }
 }