Merge tag 'v4.3-rockchip32-soc3' of git://git.kernel.org/pub/scm/linux/kernel/git...

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-rockchip / pm.c

diff --git a/arch/arm/mach-rockchip/pm.c b/arch/arm/mach-rockchip/pm.c
index 2ca1170da5d6a00ae963416a6f48a858b01b5082..bee8c80519299269cde5ba9c852243d6e5a47b05 100644 (file)
--- a/arch/arm/mach-rockchip/pm.c
+++ b/arch/arm/mach-rockchip/pm.c
@@ -123,9 +123,6 @@ static void rk3288_slp_mode_set(int level)
        regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
                     rk3288_bootram_phy);
 
-       regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
-                    PMU_ARMINT_WAKEUP_EN);
-
        mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
                   BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
                   BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
@@ -145,6 +142,22 @@ static void rk3288_slp_mode_set(int level)
 
                mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
                             BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
+
+               regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
+                            PMU_ARMINT_WAKEUP_EN);
+
+               /*
+                * In deep suspend we use PMU_PMU_USE_LF to let the rk3288
+                * switch its main clock supply to the alternative 32kHz
+                * source. Therefore set 30ms on a 32kHz clock for pmic
+                * stabilization. Similar 30ms on 24MHz for the other
+                * mode below.
+                */
+               regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30);
+
+               /* only wait for stabilization, if we turned the osc off */
+               regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT,
+                                        osc_disable ? 32 * 30 : 0);
        } else {
                /*
                 * arm off, logic normal
@@ -152,6 +165,15 @@ static void rk3288_slp_mode_set(int level)
                 * wakeup will be error
                 */
                mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);
+
+               regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
+                            PMU_ARMINT_WAKEUP_EN | PMU_GPIOINT_WAKEUP_EN);
+
+               /* 30ms on a 24MHz clock for pmic stabilization */
+               regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30);
+
+               /* oscillator is still running, so no need to wait */
+               regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 0);
        }
 
        regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
@@ -224,14 +246,14 @@ static int rk3288_suspend_init(struct device_node *np)
                                "rockchip,rk3288-sgrf");
        if (IS_ERR(sgrf_regmap)) {
                pr_err("%s: could not find sgrf regmap\n", __func__);
-               return PTR_ERR(pmu_regmap);
+               return PTR_ERR(sgrf_regmap);
        }
 
        grf_regmap = syscon_regmap_lookup_by_compatible(
                                "rockchip,rk3288-grf");
        if (IS_ERR(grf_regmap)) {
                pr_err("%s: could not find grf regmap\n", __func__);
-               return PTR_ERR(pmu_regmap);
+               return PTR_ERR(grf_regmap);
        }
 
        sram_np = of_find_compatible_node(NULL, NULL,
@@ -262,9 +284,6 @@ static int rk3288_suspend_init(struct device_node *np)
        memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
               rk3288_bootram_sz);
 
-       regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH);
-       regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH);
-
        return 0;
 }