Merge tag 'renesas-boards-cleanups2-for-v3.19' of git://git.kernel.org/pub/scm/linux...

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-socfpga / headsmp.S

diff --git a/arch/arm/mach-socfpga/headsmp.S b/arch/arm/mach-socfpga/headsmp.S
index 95c115d8b5eee5407feb99ce996f5793ceb34747..f65ea0af4af37dbdce42f9bf1af740b4feeb9e22 100644 (file)
--- a/arch/arm/mach-socfpga/headsmp.S
+++ b/arch/arm/mach-socfpga/headsmp.S
@@ -9,21 +9,26 @@
  */
 #include <linux/linkage.h>
 #include <linux/init.h>
+#include <asm/memory.h>
 
        .arch   armv7-a
 
 ENTRY(secondary_trampoline)
-       movw    r2, #:lower16:cpu1start_addr
-       movt  r2, #:upper16:cpu1start_addr
-
-       /* The socfpga VT cannot handle a 0xC0000000 page offset when loading
-               the cpu1start_addr, we bit clear it. Tested on HW and VT. */
-       bic     r2, r2, #0x40000000
-
-       ldr     r0, [r2]
-       ldr     r1, [r0]
-       bx      r1
+       /* CPU1 will always fetch from 0x0 when it is brought out of reset.
+        * Thus, we can just subtract the PAGE_OFFSET to get the physical
+        * address of &cpu1start_addr. This would not work for platforms
+        * where the physical memory does not start at 0x0.
+        */
+       adr     r0, 1f
+       ldmia   r0, {r1, r2}
+       sub     r2, r2, #PAGE_OFFSET
+       ldr     r3, [r2]
+       ldr     r4, [r3]
+       bx      r4
 
+       .align
+1:     .long   .
+       .long   socfpga_cpu1start_addr
 ENTRY(secondary_trampoline_end)
 
 ENTRY(socfpga_secondary_startup)