Merge tag 'cleanup-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git...

[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-ux500 / cpu.c

diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 002da9a369d5fe170bd2ca10658a5fa2b9a8725d..b6145ea5164105dd80a2abafffb569acbd746410 100644 (file)
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -8,7 +8,7 @@
 
 #include <linux/platform_device.h>
 #include <linux/io.h>
-#include <linux/mfd/db8500-prcmu.h>
+#include <linux/mfd/dbx500-prcmu.h>
 #include <linux/clksrc-dbx500-prcmu.h>
 #include <linux/sys_soc.h>
 #include <linux/err.h>
@@ -20,18 +20,17 @@
 #include <linux/irqchip.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-ux500.h>
+#include <linux/platform_data/arm-ux500-pm.h>
 
 #include <asm/mach/map.h>
 
-#include <mach/hardware.h>
-#include <mach/setup.h>
-#include <mach/devices.h>
+#include "setup.h"
+#include "devices.h"
 
 #include "board-mop500.h"
+#include "db8500-regs.h"
 #include "id.h"
 
-void __iomem *_PRCMU_BASE;
-
 /*
  * FIXME: Should we set up the GPIO domain here?
  *
@@ -68,13 +67,23 @@ void __init ux500_init_irq(void)
         * Init clocks here so that they are available for system timer
         * initialization.
         */
-       if (cpu_is_u8500_family() || cpu_is_u9540())
-               db8500_prcmu_early_init();
-
-       if (cpu_is_u8500_family() || cpu_is_u9540())
-               u8500_clk_init();
-       else if (cpu_is_u8540())
+       if (cpu_is_u8500_family()) {
+               prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
+               ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
+               u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+                              U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
+                              U8500_CLKRST6_BASE);
+       } else if (cpu_is_u9540()) {
+               prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
+               ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
+               u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+                              U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
+                              U8500_CLKRST6_BASE);
+       } else if (cpu_is_u8540()) {
+               prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
+               ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
                u8540_clk_init();
+       }
 }
 
 void __init ux500_init_late(void)