ARM: proc-arm94*.S: fix setup function

[firefly-linux-kernel-4.4.55.git] / arch / arm / mm / proc-arm940.S

diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index e5212d48937723e8fe711aadfba2ade276d2a442..c42cdd3b44bc675d24e8b5e9da553e79f2a5b5c1 100644 (file)
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -297,26 +297,16 @@ __arm940_setup:
        mcr     p15, 0, r0, c6, c0, 1
 
        ldr     r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
-       ldr     r1, =(CONFIG_DRAM_SIZE >> 12)   @ size of RAM (must be >= 4KB)
-       mov     r2, #10                         @ 11 is the minimum (4KB)
-1:     add     r2, r2, #1                      @ area size *= 2
-       mov     r1, r1, lsr #1
-       bne     1b                              @ count not zero r-shift
-       orr     r0, r0, r2, lsl #1              @ the area register value
-       orr     r0, r0, #1                      @ set enable bit
-       mcr     p15, 0, r0, c6, c1, 0           @ set area 1, RAM
-       mcr     p15, 0, r0, c6, c1, 1
+       ldr     r7, =CONFIG_DRAM_SIZE >> 12     @ size of RAM (must be >= 4KB)
+       pr_val  r3, r0, r7, #1
+       mcr     p15, 0, r3, c6, c1, 0           @ set area 1, RAM
+       mcr     p15, 0, r3, c6, c1, 1
 
        ldr     r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
-       ldr     r1, =(CONFIG_FLASH_SIZE >> 12)  @ size of FLASH (must be >= 4KB)
-       mov     r2, #10                         @ 11 is the minimum (4KB)
-1:     add     r2, r2, #1                      @ area size *= 2
-       mov     r1, r1, lsr #1
-       bne     1b                              @ count not zero r-shift
-       orr     r0, r0, r2, lsl #1              @ the area register value
-       orr     r0, r0, #1                      @ set enable bit
-       mcr     p15, 0, r0, c6, c2, 0           @ set area 2, ROM/FLASH
-       mcr     p15, 0, r0, c6, c2, 1
+       ldr     r7, =CONFIG_FLASH_SIZE          @ size of FLASH (must be >= 4KB)
+       pr_val  r3, r0, r6, #1
+       mcr     p15, 0, r3, c6, c2, 0           @ set area 2, ROM/FLASH
+       mcr     p15, 0, r3, c6, c2, 1
 
        mov     r0, #0x06
        mcr     p15, 0, r0, c2, c0, 0           @ Region 1&2 cacheable