Merge tag 'lsk-android-14.03' into develop-3.10

[firefly-linux-kernel-4.4.55.git] / arch / arm / mm / proc-v7.S

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index e35fec34453ea13d57e2f1902a07bc99e21ba731..784df09cd118469346de0924d3516977cf43b850 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -75,13 +75,14 @@ ENTRY(cpu_v7_do_idle)
 ENDPROC(cpu_v7_do_idle)
 
 ENTRY(cpu_v7_dcache_clean_area)
-       ALT_SMP(mov     pc, lr)                 @ MP extensions imply L1 PTW
-       ALT_UP(W(nop))
-       dcache_line_size r2, r3
-1:     mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
+       ALT_SMP(W(nop))                 @ MP extensions imply L1 PTW
+       ALT_UP_B(1f)
+       mov     pc, lr
+1:     dcache_line_size r2, r3
+2:     mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, r2
        subs    r1, r1, r2
-       bhi     1b
+       bhi     2b
        dsb
        mov     pc, lr
 ENDPROC(cpu_v7_dcache_clean_area)
@@ -181,6 +182,7 @@ __v7_ca9mp_setup:
        mov     r10, #(1 << 0)                  @ TLB ops broadcasting
        b       1f
 __v7_ca7mp_setup:
+__v7_ca12mp_setup:
 __v7_ca15mp_setup:
        mov     r10, #0
 1:
@@ -328,7 +330,6 @@ __v7_setup:
 
 3:     mov     r10, #0
        mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
-       dsb
 #ifdef CONFIG_MMU
        mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
        v7_ttb_setup r10, r4, r8, r5            @ TTBCR, TTBRx setup
@@ -337,6 +338,7 @@ __v7_setup:
        mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
        mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
 #endif
+       dsb                                     @ Complete invalidations
 #ifndef CONFIG_ARM_THUMBEE
        mrc     p15, 0, r0, c0, c1, 0           @ read ID_PFR0 for ThumbEE
        and     r0, r0, #(0xf << 12)            @ ThumbEE enabled field
@@ -452,6 +454,16 @@ __v7_ca7mp_proc_info:
        __v7_proc __v7_ca7mp_setup
        .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
 
+       /*
+        * ARM Ltd. Cortex A12 processor.
+        */
+       .type   __v7_ca12mp_proc_info, #object
+__v7_ca12mp_proc_info:
+       .long   0x410fc0d0
+       .long   0xff0ffff0
+       __v7_proc __v7_ca12mp_setup
+       .size   __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
+
        /*
         * ARM Ltd. Cortex A15 processor.
         */