RK3368: spi: spi0 2csn,spi1 2csn,sp2 1csn in dts config

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rk3368.dtsi

diff --git a/arch/arm64/boot/dts/rk3368.dtsi b/arch/arm64/boot/dts/rk3368.dtsi
index 2c7874fa83c37eff1a45979c5de95774b0cf0185..288de670d65b405d6c3efa4636b900d1c2cf475d 100755 (executable)
--- a/arch/arm64/boot/dts/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rk3368.dtsi
@@ -37,53 +37,72 @@
                #address-cells = <2>;
                #size-cells = <0>;
 
-               big0: cpu@100 {
+               idle-states {
+                       entry-method = "arm,psci";
+                       CPU_SLEEP_0: cpu-sleep-0 {
+                               compatible = "arm,idle-state";
+                               arm,psci-suspend-param = <0x0000000>;
+                               entry-latency-us = <10000000>;
+                               exit-latency-us = <10000000>;
+                               min-residency-us = <25000>;
+                       };
+               };
+
+               little0: cpu@100 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                };
-               big1: cpu@101 {
+               little1: cpu@101 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x101>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                };
-               big2: cpu@102 {
+               little2: cpu@102 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x102>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                };
-               big3: cpu@103 {
+               little3: cpu@103 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x103>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                };
-               little0: cpu@0 {
+               big0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                };
-               little1: cpu@1 {
+               big1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                };
-               little2: cpu@2 {
+               big2: cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                };
-               little3: cpu@3 {
+               big3: cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53", "arm,armv8";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_0>;
                };
 
                cpu-map {
@@ -119,9 +138,8 @@
        };
 
        psci {
-               compatible = "arm,psci";
+               compatible = "arm,psci-0.2";
                method = "smc";
-               cpu_on = <0xC4000003>;
        };
 
        gic: interrupt-controller@ffb70000 {
@@ -188,6 +206,9 @@
                        crypto {
                                reg = <0x0 0xffa80080 0x0 0x20>;
                        };
+                       tsp {
+                               reg = <0x0 0xffa80280 0x0 0x20>;
+                       };
                        bus_cpup {
                                reg = <0x0 0xffa90000 0x0 0x20>;
                        };
@@ -199,6 +220,7 @@
                        };
                        peri {
                                reg = <0x0 0xffab0000 0x0 0x20>;
+                               rockchip,priority = <2 2>;
                        };
                        iep {
                                reg = <0x0 0xffad0000 0x0 0x20>;
@@ -234,10 +256,13 @@
                                reg = <0x0 0xffae0000 0x0 0x20>;
                        };
                        vpu_r {
-                               reg = <0x0 0xffae0080 0x0 0x20>;
+                               reg = <0x0 0xffae0100 0x0 0x20>;
                        };
                        vpu_w {
-                               reg = <0x0 0xffae0100 0x0 0x20>;
+                               reg = <0x0 0xffae0180 0x0 0x20>;
+                       };
+                       gpu {
+                               reg = <0x0 0xffaf0000 0x0 0x20>;
                        };
                };
 
@@ -413,9 +438,9 @@
                #address-cells = <1>;
                #size-cells = <0>;
                pinctrl-names = "default";
-               pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
+               pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
                rockchip,spi-src-clk = <1>;
-               num-cs = <1>;
+               num-cs = <2>;
                clocks = <&clk_spi1>, <&clk_gates19 5>;
                clock-names = "spi", "pclk_spi1";
                //dmas = <&pdma1 13>, <&pdma1 14>;
@@ -582,6 +607,7 @@
                        <&clk_gates12 5>,/*aclk_intmem0*/
                        <&clk_gates12 4>,/*aclk_intmem*/
                        <&clk_gates13 9>,/*aclk_gic400*/
+                       <&clk_gates12 9>,/*hclk_rom*/
 
                        /*PD_ALIVE*/
                        <&clk_gates22 13>,/*pclk_timer1*/
@@ -727,8 +753,8 @@
                rockchip,grf = <&grf>;
                reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
                reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
-               clocks = <&clk_gates22 10>, <&clk_gates17 3>;
-               clock-names = "pclk_lvds", "pclk_lvds_ctl";
+               clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
+               clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
                status = "disabled";
        };
 
@@ -779,8 +805,8 @@
                 *pinctrl-1 = <&lcdc_gpio>;
                 */
                 status = "disabled";
-                clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
-                clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
+                clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
+                clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
        };
 
        adc: adc@ff100000 {
@@ -1047,7 +1073,7 @@
                iommu_enabled = <0>;
                reg = <0x0 0xff900000 0x0 0x800>;
                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&clk_gates15 2>, <&clk_gates15 3>;
+               clocks = <&clk_gates16 2>, <&clk_gates16 3>;
                clock-names = "aclk_iep", "hclk_iep";
                status = "okay";
        };
@@ -1165,8 +1191,8 @@
                compatible = "rockchip,isp";
                reg = <0x0 0xff910000 0x0 0x10000>;
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>;
-               clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx";
+               clocks = <&clk_gates17 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>,<&clk_gates16 0>;
+               clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "aclk_rga";
                pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
                pinctrl-0 = <&cif_clkout>;
                pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
@@ -1597,6 +1623,9 @@
                        spi1_tx: spi1-tx {
                                rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
                        };
+                       spi1_cs1: spi1-cs1 {
+                               rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
+                       };
                };
 
                spi2 {