RK3368: spi: spi0 2csn,spi1 2csn,sp2 1csn in dts config

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rk3368.dtsi

diff --git a/arch/arm64/boot/dts/rk3368.dtsi b/arch/arm64/boot/dts/rk3368.dtsi
index b78cfcd3bde3553d6454296dfca8ca185247c372..288de670d65b405d6c3efa4636b900d1c2cf475d 100755 (executable)
--- a/arch/arm64/boot/dts/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rk3368.dtsi
@@ -438,9 +438,9 @@
                #address-cells = <1>;
                #size-cells = <0>;
                pinctrl-names = "default";
-               pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
+               pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
                rockchip,spi-src-clk = <1>;
-               num-cs = <1>;
+               num-cs = <2>;
                clocks = <&clk_spi1>, <&clk_gates19 5>;
                clock-names = "spi", "pclk_spi1";
                //dmas = <&pdma1 13>, <&pdma1 14>;
@@ -753,8 +753,8 @@
                rockchip,grf = <&grf>;
                reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
                reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
-               clocks = <&clk_gates22 10>, <&clk_gates17 3>;
-               clock-names = "pclk_lvds", "pclk_lvds_ctl";
+               clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
+               clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
                status = "disabled";
        };
 
@@ -805,8 +805,8 @@
                 *pinctrl-1 = <&lcdc_gpio>;
                 */
                 status = "disabled";
-                clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
-                clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
+                clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
+                clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
        };
 
        adc: adc@ff100000 {
@@ -1623,6 +1623,9 @@
                        spi1_tx: spi1-tx {
                                rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
                        };
+                       spi1_cs1: spi1-cs1 {
+                               rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
+                       };
                };
 
                spi2 {