#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/display/rk_fb.h>
#include <dt-bindings/display/mipi_dsi.h>
#include <dt-bindings/power/rk3366-power.h>
-#include <dt-bindings/soc/rockchip_boot-mode.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/display/drm_mipi_dsi.h>
+#include <dt-bindings/display/media-bus-format.h>
/ {
compatible = "rockchip,rk3366";
compatible = "operating-points-v2";
opp-shared;
- opp00 {
+ nvmem-cells = <&cpu_leakage>;
+ nvmem-cell-names = "cpu_leakage";
+
+ opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
opp-suspend;
};
- opp01 {
+ opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000>;
};
- opp02 {
+ opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1000000>;
};
- opp03 {
+ opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1075000>;
};
- opp04 {
+ opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1175000>;
};
- opp05 {
+ opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1250000>;
};
status = "disabled";
};
- sdmmc: rksdmmc@ff400000 {
+ sdmmc: dwmmc@ff400000 {
compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
status = "disabled";
};
- sdio: rksdmmc@ff410000 {
+ sdio: dwmmc@ff410000 {
compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
status = "disabled";
};
- emmc: rksdmmc@ff420000 {
+ emmc: dwmmc@ff420000 {
compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
status = "disabled";
};
- usbphy: phy {
- compatible = "rockchip,rk336x-usb-phy";
- rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- usbphy0: usb-phy0 {
- #phy-cells = <0>;
- #clock-cells = <0>;
- reg = <0x700>;
- };
-
- usbphy1: usb-phy1 {
- #phy-cells = <0>;
- #clock-cells = <0>;
- reg = <0x728>;
- };
- };
-
- usb_host0_echi: usb@ff480000 {
+ usb_host0_ehci: usb@ff480000 {
compatible = "generic-ehci";
reg = <0x0 0xff480000 0x0 0x20000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
- clock-names = "sclk_otgphy0", "hclk_host0";
- phys = <&usbphy1>;
+ clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
+ clock-names = "usbphy_480m", "hclk_host0";
+ phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
};
compatible = "generic-ohci";
reg = <0x0 0xff4a0000 0x0 0x20000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
- clock-names = "sclk_otgphy0", "hclk_host0";
+ clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
+ clock-names = "usbphy_480m", "hclk_host0";
+ phys = <&u2phy_host>;
+ phy-names = "usb";
status = "disabled";
};
status = "disabled";
};
+ efuse: efuse@ff670000 {
+ compatible = "rockchip,rk3366-efuse";
+ reg = <0x0 0xff670000 0x0 0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru PCLK_EFUSE_256>;
+ clock-names = "pclk_efuse";
+
+ /* Data cells */
+ cpu_leakage: cpu-leakage {
+ reg = <0x17 0x1>;
+ };
+ gpu_leakage: gpu-leakage {
+ reg = <0x18 0x1>;
+ };
+ logic_leakage: logic-leakage {
+ reg = <0x19 0x1>;
+ };
+ wafer_info: wafer-info {
+ reg = <0x1c 0x1>;
+ };
+ };
+
pwm0: pwm@ff680000 {
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
reg = <0x0 0xff680000 0x0 0x10>;
reg = <0x0 0xff730000 0x0 0x1000>;
power: power-controller {
- status = "disabled";
compatible = "rockchip,rk3366-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
* synchronous reset.
*
* The clocks on the which NOC:
- * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
- * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
- * ACLK_ISP is on ACLK_ISP_NIU.
- * ACLK_HDCP is on ACLK_HDCP_NIU.
- * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
+ * ACLK_IEP/ACLK_VOP_FULL are on ACLK_VIO0_NOC.
+ * ACLK_RGA/ACLK_VOP_LITE are on ACLK_VIO1_NOC.
+ * ACLK_ISP is on ACLK_ISP_NOC.
+ * ACLK_HDCP is on ACLK_HDCP_NOC.
+ * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NOC.
*
* Which clock are device clocks:
* clocks devices
* *_RGA RGA
* *_DPHY* LVDS
* *_HDMI HDMI
- * *_MIPI_* MIPI
+ * *_MIPI_* MIPI/LVDS
*/
- pd_vio {
+ pd_vio@RK3366_PD_VIO {
reg = <RK3366_PD_VIO>;
clocks = <&cru ACLK_IEP>,
<&cru ACLK_ISP>,
<&cru HCLK_VOP_FULL>,
<&cru HCLK_VOP_LITE>,
<&cru HCLK_VIO_HDCPMMU>,
+ <&cru PCLK_DPHYTX>,
<&cru PCLK_HDMI_CTRL>,
<&cru PCLK_HDCP>,
<&cru PCLK_MIPI_DSI0>,
};
/*
- * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
- * (video endecoder & decoder) clocks that on the
- * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
+ * Note: ACLK_VCODEC/HCLK_VCODEC are VPU clocks
+ * that on the ACLK_VCODEC_NOC and
+ * HCLK_VCODEC_NOC.
*/
- pd_vpu {
+ pd_vpu@RK3366_PD_VPU {
reg = <RK3366_PD_VPU>;
clocks = <&cru ACLK_VIDEO>,
<&cru HCLK_VIDEO>;
/*
* Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
- * (video decoder) clocks that on the
- * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
+ * clocks that on the ACLK_RKVDEC_NOC and
+ * HCLK_RKVDEC_NOC.
*/
- pd_rkvdec {
+ pd_rkvdec@RK3366_PD_RKVDEC {
reg = <RK3366_PD_RKVDEC>;
clocks = <&cru ACLK_RKVDEC>,
- <&cru HCLK_RKVDEC>;
- };
-
- pd_video {
- reg = <RK3366_PD_VIDEO>;
- clocks = <&cru ACLK_VIDEO>,
- <&cru ACLK_RKVDEC>,
- <&cru HCLK_VIDEO>,
<&cru HCLK_RKVDEC>,
<&cru SCLK_HEVC_CABAC>,
<&cru SCLK_HEVC_CORE>;
};
/*
- * Note: ACLK_GPU is the GPU clock,
- * and on the ACLK_GPU_NIU (NOC).
+ * Note: ACLK_GPU is the GPU clock
+ * that on the ACLK_GPU_NOC.
*/
- pd_gpu {
+ pd_gpu@RK3366_PD_GPU {
reg = <RK3366_PD_GPU>;
clocks = <&cru ACLK_GPU>;
};
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-fastboot = <BOOT_FASTBOOT>;
- mode-loader = <BOOT_LOADER>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ };
+
+ pmu_pvtm: pmu-pvtm {
+ compatible = "rockchip,rk3366-pmu-pvtm";
+ clocks = <&cru SCLK_PVTM_PMU>;
+ clock-names = "pmu";
+ status = "disabled";
};
};
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC_PERI>;
clock-names = "apb_pclk";
+ peripherals-req-type-burst;
};
dmac_bus: dma-controller@ff600000 {
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC_BUS>;
clock-names = "apb_pclk";
+ peripherals-req-type-burst;
};
};
assigned-clocks =
<&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
<&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
+ <&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>,
+ <&cru SCLK_SPDIF_8CH_SRC>,
<&cru PLL_CPLL>, <&cru PLL_GPLL>,
<&cru PLL_NPLL>, <&cru PLL_MPLL>,
<&cru PLL_WPLL>, <&cru PLL_BPLL>,
assigned-clock-rates =
<0>, <0>,
<0>, <0>,
+ <0>, <0>,
+ <0>,
<750000000>, <576000000>,
<594000000>, <594000000>,
<960000000>, <520000000>,
<144000000>;
assigned-clock-parents =
<&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
- <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
+ <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>,
+ <&cru PLL_GPLL>, <&cru PLL_GPLL>,
+ <&cru PLL_GPLL>;
};
grf: syscon@ff770000 {
- compatible = "rockchip,rk3366-grf", "syscon";
+ compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy: usb2-phy@700 {
+ compatible = "rockchip,rk3366-usb2phy";
+ reg = <0x700 0x2c>;
+ clocks = <&cru SCLK_OTG_PHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "sclk_otgphy0_480m";
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "okay";
+ };
+ };
+
+ pvtm: pvtm {
+ compatible = "rockchip,rk3366-pvtm";
+ clocks = <&cru SCLK_PVTM_CORE>, <&cru SCLK_PVTM_GPU>;
+ clock-names = "core", "gpu";
+ status = "disabled";
+ };
};
wdt: watchdog@ff800000 {
status = "disabled";
};
+ rktimer: rktimer@ff810000 {
+ compatible = "rockchip,rk3288-timer";
+ reg = <0x0 0xff810000 0x0 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER0>;
+ clock-names = "pclk", "timer";
+ };
+
spdif: spdif@ff880000 {
compatible = "rockchip,rk3366-spdif";
reg = <0x0 0xff880000 0x0 0x1000>;
status = "disabled";
};
- fb: fb {
- compatible = "rockchip,rk-fb";
- rockchip,disp-mode = <DUAL>;
- status = "disabled";
- };
-
- rk_screen: screen {
- compatible = "rockchip,screen";
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vopb_out>, <&vopl_out>;
status = "disabled";
};
- vop_lite: vop@ff8f0000 {
- compatible = "rockchip,rk3366-lcdc-lite";
- rockchip,grf = <&grf>;
- rockchip,pwr18 = <0>;
- rockchip,iommu-enabled = <1>;
- reg = <0x0 0xff8f0000 0x0 0x1000>;
+ vopl: vop@ff8f0000 {
+ compatible = "rockchip,rk3366-vop-lit";
+ reg = <0x0 0xff8f0000 0x0 0x900>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
- clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
- resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
+ clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>,
+ <&cru HCLK_VOP_LITE>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>,
+ <&cru SRST_VOP1_AHB>;
reset-names = "axi", "ahb", "dclk";
+ power-domains = <&power RK3366_PD_VIO>;
+ iommus = <&vopl_mmu>;
status = "disabled";
+
+ vopl_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vopl_out_dsi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_in_vopl>;
+ };
+
+ vopl_out_lvds: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&lvds_in_vopl>;
+ };
+ };
};
- vopl_mmu: vopl-mmu {
- dbgname = "vop";
- compatible = "rockchip,vopl_mmu";
+ vopl_mmu: iommu@ff8f0f00 {
+ compatible = "rockchip,iommu";
reg = <0x0 0xff8f0f00 0x0 0x100>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopl_mmu";
+ clocks = <&cru ACLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3366_PD_VIO>;
+ #iommu-cells = <0>;
status = "disabled";
};
iep: iep@ff900000 {
compatible = "rockchip,iep";
iommu_enabled = <1>;
+ iommus = <&iep_mmu>;
reg = <0x0 0xff900000 0x0 0x800>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk_iep", "hclk_iep";
+ power-domains = <&power RK3366_PD_VIO>;
+ allocator = <1>;
version = <2>;
status = "disabled";
};
+ iep_mmu: iommu@ff900800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff900800 0x0 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep_mmu";
+ power-domains = <&power RK3366_PD_VIO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
rga: rga@ff920000 {
compatible = "rockchip,rga2";
dev_mode = <1>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
clock-names = "aclk_rga", "hclk_rga", "clk_rga";
+ power-domains = <&power RK3366_PD_VIO>;
status = "disabled";
};
- vop_big: vop@ff930000 {
- compatible = "rockchip,rk3366-lcdc-big";
- rockchip,grf = <&grf>;
- rockchip,prop = <PRMRY>;
- rockchip,pwr18 = <0>;
- rockchip,iommu-enabled = <1>;
- reg = <0x0 0xff930000 0x0 0x23f0>;
+ vopb: vop@ff930000 {
+ compatible = "rockchip,rk3366-vop";
+ reg = <0x0 0xff930000 0x0 0x1ffc>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
- clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
- resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
+ clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>,
+ <&cru HCLK_VOP_FULL>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ power-domains = <&power RK3366_PD_VIO>;
+ resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>,
+ <&cru SRST_VOP0_AHB>;
reset-names = "axi", "ahb", "dclk";
+ iommus = <&vopb_mmu>;
status = "disabled";
+
+ vopb_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vopb_out_dsi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dsi_in_vopb>;
+ };
+
+ vopb_out_lvds: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&lvds_in_vopb>;
+ };
+
+ vopb_out_hdmi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&hdmi_in_vopb>;
+ };
+ };
};
- vopb_mmu: vopb-mmu {
- dbgname = "vop";
- compatible = "rockchip,vopb_mmu";
+ vopb_mmu: iommu@ff932400 {
+ compatible = "rockchip,iommu";
reg = <0x0 0xff932400 0x0 0x100>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vop_mmu";
+ clocks = <&cru ACLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3366_PD_VIO>;
+ #iommu-cells = <0>;
status = "disabled";
};
- iep_mmu: iep-mmu {
- dbgname = "iep";
- compatible = "rockchip,iep_mmu";
- reg = <0x0 0xff900800 0x0 0x100>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "iep_mmu";
+ dsi: dsi@ff960000 {
+ compatible = "rockchip,rk3366-mipi-dsi";
+ reg = <0x0 0xff960000 0x0 0x4000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>;
+ clock-names = "pclk", "hs_clk";
+ resets = <&cru SRST_MIPIDSI0>;
+ reset-names = "apb";
+ phys = <&mipi_dphy>;
+ phy-names = "mipi_dphy";
+ power-domains = <&power RK3366_PD_VIO>;
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
- };
- vpu_mmu: vpu_mmu {
- dbgname = "vpu";
- compatible = "rockchip,vpu_mmu";
- reg = <0x0 0xff9a0800 0x0 0x100>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vpu_mmu";
- status = "disabled";
- };
+ ports {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
- vdec_mmu: vdec_mmu {
- dbgname = "vdec";
- compatible = "rockchip,vdec_mmu";
- reg = <0x0 0xff9b0480 0x0 0x40>,
- <0x0 0xff9b04c0 0x0 0x40>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vdec_mmu";
- status = "disabled";
+ dsi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_dsi>;
+ };
+ dsi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_dsi>;
+ };
+ };
+ };
};
- dsihost0: mipi@ff960000 {
- compatible = "rockchip,rk3366-dsi";
- rockchip,prop = <0>;
- reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
- reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
- clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
+ mipi_dphy: mipi-dphy@ff968000 {
+ compatible = "rockchip,rk3366-mipi-dphy";
+ reg = <0x0 0xff968000 0x0 0x4000>;
+ clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>;
+ clock-names = "ref", "pclk";
+ clock-output-names = "mipi_dphy_pll";
+ #clock-cells = <0>;
+ resets = <&cru SRST_MIPIDPHYTX>;
+ reset-names = "apb";
+ #phy-cells = <0>;
status = "disabled";
};
lvds: lvds@ff968000 {
compatible = "rockchip,rk3366-lvds";
- rockchip,grf = <&grf>;
reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
clock-names = "pclk_lvds", "pclk_lvds_ctl";
+ power-domains = <&power RK3366_PD_VIO>;
+ pinctrl-names = "lcdc", "gpio";
+ pinctrl-0 = <&lcdc_lcdc>;
+ pinctrl-1 = <&lcdc_gpio>;
+ rockchip,grf = <&grf>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lvds_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_lvds>;
+ };
+ lvds_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_lvds>;
+ };
+ };
+ };
+
};
hdmi: hdmi@ff980000 {
- compatible = "rockchip,rk3366-hdmi";
+ compatible = "rockchip,rk3366-dw-hdmi";
reg = <0x0 0xff980000 0x0 0x20000>;
+ reg-io-width = <4>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMI_CTRL>,
- <&cru SCLK_HDMI_HDCP>,
- <&cru SCLK_HDMI_CEC>,
- <&cru DCLK_HDMIPHY>;
- clock-names = "pclk_hdmi",
- "hdcp_clk_hdmi",
- "cec_clk_hdmi",
- "dclk_hdmi_phy";
+ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>,
+ <&cru SCLK_HDMI_CEC>, <&cru DCLK_HDMIPHY>;
+ clock-names = "iahb", "isfr", "cec", "dclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
resets = <&cru SRST_HDMI>;
reset-names = "hdmi";
- pinctrl-names = "default", "gpio";
- pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
- pinctrl-1 = <&i2c5_gpio>;
+ //power-domains = <&power RK3366_PD_VIO>;
+ rockchip,grf = <&grf>;
status = "disabled";
+
+ ports {
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_hdmi>;
+ };
+ };
+ };
};
vpu: vpu_service@ff9a0000 {
compatible = "rockchip,vpu_service";
rockchip,grf = <&grf>;
iommu_enabled = <1>;
+ iommus = <&vpu_mmu>;
reg = <0x0 0xff9a0000 0x0 0x800>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec", "irq_enc";
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
clock-names = "aclk_vcodec", "hclk_vcodec";
+ power-domains = <&power RK3366_PD_VPU>;
resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
reset-names = "video_h", "video_a";
name = "vpu_service";
dev_mode = <0>;
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ status = "disabled";
+ };
+
+ vpu_mmu: iommu@ff9a0800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9a0800 0x0 0x100>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vpu_mmu";
+ clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3366_PD_VPU>;
+ #iommu-cells = <0>;
status = "disabled";
};
rkvdec: rkvdec@ff9b0000 {
compatible = "rockchip,rkvdec";
rockchip,grf = <&grf>;
+ iommus = <&vdec_mmu>;
iommu_enabled = <1>;
reg = <0x0 0xff9b0000 0x0 0x400>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
+ power-domains = <&power RK3366_PD_RKVDEC>;
resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
reset-names = "video_h", "video_a";
dev_mode = <2>;
name = "rkvdec";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ status = "disabled";
+ };
+
+ vdec_mmu: iommu@ff9b0480 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff9b0480 0x0 0x40>,
+ <0x0 0xff9b04c0 0x0 0x40>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vdec_mmu";
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3366_PD_RKVDEC>;
+ #iommu-cells = <0>;
status = "disabled";
};
<0 22 RK_FUNC_2 &pcfg_pull_none>;
};
};
+
+ usb2 {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins =
+ <0 16 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
};
gpu: gpu@ffa30000 {
clocks = <&cru ACLK_GPU>;
clock-names = "clk_mali";
#cooling-cells = <2>; /* min followed by max */
+ power-domains = <&power RK3366_PD_GPU>;
operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
compatible = "operating-points-v2";
opp-shared;
- opp00 {
+ opp-96000000 {
opp-hz = /bits/ 64 <96000000>;
opp-microvolt = <1100000>;
};
- opp01 {
+ opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
opp-microvolt = <1100000>;
};
- opp02 {
+ opp-288000000 {
opp-hz = /bits/ 64 <288000000>;
opp-microvolt = <1100000>;
};
- opp03 {
+ opp-375000000 {
opp-hz = /bits/ 64 <375000000>;
opp-microvolt = <1125000>;
};
- opp04 {
+ opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-microvolt = <1200000>;
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff