arm64: dts: rockchip: rk3366: export MIPI DPHY PLL clock

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3366.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index f583cffd49490216f6978ba9893e809b3e3d626c..47388e8cdb13ce0130aaf8c5547e627bd9bab438 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -828,6 +828,14 @@
                status = "disabled";
        };
 
+       rktimer: rktimer@ff810000 {
+               compatible = "rockchip,rk3288-timer";
+               reg = <0x0 0xff810000 0x0 0x1000>;
+               interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER0>;
+               clock-names = "pclk", "timer";
+       };
+
        spdif: spdif@ff880000 {
                compatible = "rockchip,rk3366-spdif";
                reg = <0x0 0xff880000 0x0 0x1000>;
@@ -867,16 +875,46 @@
 
        display_subsystem: display-subsystem {
                compatible = "rockchip,display-subsystem";
-               ports = <&vopb_out>;
+               ports = <&vopb_out>, <&vopl_out>;
                status = "disabled";
        };
 
-       vopb_mmu: iommu@ff8f3f00 {
+       vopl: vop@ff8f0000 {
+               compatible = "rockchip,rk3366-vop-lit";
+               reg = <0x0 0xff8f0000 0x0 0x900>;
+               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>,
+                        <&cru HCLK_VOP_LITE>;
+               clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+               resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>,
+                        <&cru SRST_VOP1_AHB>;
+               reset-names = "axi", "ahb", "dclk";
+               power-domains = <&power RK3366_PD_VIO>;
+               iommus = <&vopl_mmu>;
+               status = "disabled";
+
+               vopl_out: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       vopl_out_dsi: endpoint@0 {
+                               reg = <0>;
+                               remote-endpoint = <&dsi_in_vopl>;
+                       };
+
+                       vopl_out_lvds: endpoint@1 {
+                               reg = <1>;
+                               remote-endpoint = <&lvds_in_vopl>;
+                       };
+               };
+       };
+
+       vopl_mmu: iommu@ff8f0f00 {
                compatible = "rockchip,iommu";
-               reg = <0x0 0xff932400 0x0 0x100>;
-               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
-               interrupt-names = "vop_mmu";
-               clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>;
+               reg = <0x0 0xff8f0f00 0x0 0x100>;
+               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>;
+               interrupt-names = "vopl_mmu";
+               clocks = <&cru ACLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
                clock-names = "aclk", "hclk";
                power-domains = <&power RK3366_PD_VIO>;
                #iommu-cells = <0>;
@@ -953,12 +991,24 @@
                };
        };
 
+       vopb_mmu: iommu@ff932400 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff932400 0x0 0x100>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
+               interrupt-names = "vop_mmu";
+               clocks = <&cru ACLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
+               clock-names = "aclk", "hclk";
+               power-domains = <&power RK3366_PD_VIO>;
+               #iommu-cells = <0>;
+               status = "disabled";
+       };
+
        dsi: dsi@ff960000 {
                compatible = "rockchip,rk3366-mipi-dsi";
                reg = <0x0 0xff960000 0x0 0x4000>;
                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru PCLK_MIPI_DSI0>;
-               clock-names = "pclk";
+               clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>;
+               clock-names = "pclk", "hs_clk";
                resets = <&cru SRST_MIPIDSI0>;
                reset-names = "apb";
                phys = <&mipi_dphy>;
@@ -978,6 +1028,10 @@
                                        reg = <0>;
                                        remote-endpoint = <&vopb_out_dsi>;
                                };
+                               dsi_in_vopl: endpoint@1 {
+                                       reg = <1>;
+                                       remote-endpoint = <&vopl_out_dsi>;
+                               };
                        };
                };
        };
@@ -987,6 +1041,8 @@
                reg = <0x0 0xff968000 0x0 0x4000>;
                clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>;
                clock-names = "ref", "pclk";
+               clock-output-names = "mipi_dphy_pll";
+               #clock-cells = <0>;
                resets = <&cru SRST_MIPIDPHYTX>;
                reset-names = "apb";
                #phy-cells = <0>;
@@ -1019,6 +1075,10 @@
                                        reg = <0>;
                                        remote-endpoint = <&vopb_out_lvds>;
                                };
+                               lvds_in_vopl: endpoint@1 {
+                                       reg = <1>;
+                                       remote-endpoint = <&vopl_out_lvds>;
+                               };
                        };
                };