arm64: dts: rockchip: rk3368: revert xin32k use the fixed clk

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3368.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 10e816e84134f050f89ed46bd25c67651a46e6a6..aa175a0d151925d0f199839c653190769ce69643 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -473,13 +473,6 @@
                #clock-cells = <0>;
        };
 
-       xin32k: xin32k {
-               compatible = "fixed-clock";
-               clock-frequency = <32768>;
-               clock-output-names = "xin32k";
-               #clock-cells = <0>;
-       };
-
        sdmmc: dwmmc@ff0c0000 {
                compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x0 0xff0c0000 0x0 0x4000>;
@@ -747,6 +740,7 @@
                nvmem-cell-names = "temp_adjust";
                #thermal-sensor-cells = <1>;
                hw-shut-temp = <95000>;
+               latency-bound = <50000>;
                status = "disabled";
        };
 
@@ -1119,12 +1113,14 @@
                        <&cru PLL_GPLL>, <&cru PLL_CPLL>,
                        <&cru ACLK_BUS>, <&cru ACLK_PERI>,
                        <&cru HCLK_BUS>, <&cru HCLK_PERI>,
-                       <&cru PCLK_BUS>, <&cru PCLK_PERI>;
+                       <&cru PCLK_BUS>, <&cru PCLK_PERI>,
+                       <&cru ACLK_CCI_PRE>;
                assigned-clock-rates =
                        <576000000>, <400000000>,
                        <300000000>, <300000000>,
                        <150000000>, <150000000>,
-                       <75000000>, <75000000>;
+                       <75000000>, <75000000>,
+                       <576000000>;
        };
 
        grf: syscon@ff770000 {
@@ -1206,6 +1202,30 @@
                status = "disabled";
        };
 
+       iep: iep@ff900000 {
+               compatible = "rockchip,iep";
+               iommu_enabled = <1>;
+               iommus = <&iep_mmu>;
+               reg = <0x0 0xff900000 0x0 0x800>;
+               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+               clock-names = "aclk_iep", "hclk_iep";
+               power-domains = <&power RK3368_PD_VIO>;
+               allocator = <1>;
+               version = <2>;
+               status = "disabled";
+       };
+
+       iep_mmu: iommu@ff900800 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff900800 0x0 0x100>;
+               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
+               interrupt-names = "iep_mmu";
+               power-domains = <&power RK3368_PD_VIO>;
+               #iommu-cells = <0>;
+               status = "disabled";
+       };
+
        isp: isp@ff910000 {
                compatible = "rockchip,rk3368-isp", "rockchip,isp";
                reg = <0x0 0xff910000 0x0 0x4000>;
@@ -1317,6 +1337,8 @@
                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru PCLK_MIPI_DSI0>;
                clock-names = "pclk";
+               resets = <&cru SRST_MIPIDSI0>;
+               reset-names = "apb";
                phys = <&mipi_dphy>;
                phy-names = "mipi_dphy";
                rockchip,grf = <&grf>;
@@ -1325,17 +1347,9 @@
                #size-cells = <0>;
                status = "disabled";
 
-               ports@1 {
-                       #address-cells = <1>;
-                       #size-cells = <0>;
-                       reg = <1>;
-
-                       mipi_in: port {
-                               #address-cells = <1>;
-                               #size-cells = <0>;
-
-                               mipi_in_vop: endpoint@0 {
-                                       reg = <0>;
+               ports {
+                       port {
+                               mipi_in_vop: endpoint {
                                        remote-endpoint = <&vop_out_mipi>;
                                };
                        };
@@ -1348,6 +1362,8 @@
                #phy-cells = <0>;
                clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
                clock-names = "ref", "pclk";
+               resets = <&cru SRST_MIPIDPHYTX>;
+               reset-names = "apb";
                status = "disabled";
        };