compatible = "rockchip,rk3368-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_MIPI_DSI0>;
- clock-names = "pclk";
+ clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>;
+ clock-names = "pclk", "hs_clk";
resets = <&cru SRST_MIPIDSI0>;
reset-names = "apb";
phys = <&mipi_dphy>;
mipi_dphy: mipi-dphy@ff968000 {
compatible = "rockchip,rk3368-mipi-dphy";
reg = <0x0 0xff968000 0x0 0x4000>;
- #phy-cells = <0>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
clock-names = "ref", "pclk";
+ clock-output-names = "mipi_dphy_pll";
+ #clock-cells = <0>;
resets = <&cru SRST_MIPIDPHYTX>;
reset-names = "apb";
+ #phy-cells = <0>;
status = "disabled";
};
lvds: lvds@ff968000 {
compatible = "rockchip,rk3368-lvds";
- reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
+ reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff960000 0x0 0x100>;
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
clock-names = "pclk_lvds", "pclk_lvds_ctl";