#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3368-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/soc/rockchip-system-status.h>
+#include <dt-bindings/suspend/rockchip-rk3368.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/display/mipi_dsi.h>
#include <dt-bindings/display/drm_mipi_dsi.h>
#include <dt-bindings/display/media-bus-format.h>
+#include "rk3368-dram-default-timing.dtsi"
+
/ {
compatible = "rockchip,rk3368";
interrupt-parent = <&gic>;
};
};
- idle-states {
- entry-method = "psci";
-
- cpu_sleep: cpu-sleep-0 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x1010000>;
- entry-latency-us = <0x3fffffff>;
- exit-latency-us = <0x40000000>;
- min-residency-us = <0xffffffff>;
- };
- };
-
cpu_l0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ next-level-cache = <&cluster0_l2>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
#cooling-cells = <2>; /* min followed by max */
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ next-level-cache = <&cluster0_l2>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ next-level-cache = <&cluster0_l2>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
+ next-level-cache = <&cluster0_l2>;
operating-points-v2 = <&cluster0_opp>;
sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
};
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x100>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ next-level-cache = <&cluster1_l2>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
#cooling-cells = <2>; /* min followed by max */
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x101>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ next-level-cache = <&cluster1_l2>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x102>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ next-level-cache = <&cluster1_l2>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x103>;
- cpu-idle-states = <&cpu_sleep>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
+ next-level-cache = <&cluster1_l2>;
operating-points-v2 = <&cluster1_opp>;
sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
};
+
+ cluster0_l2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ cluster1_l2: l2-cache1 {
+ compatible = "cache";
+ };
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
-
- opp@216000000 {
+ leakage-voltage-sel = <
+ 1 24 0
+ 25 254 1
+ >;
+ nvmem-cells = <&cpu_leakage>;
+ nvmem-cell-names = "cpu_leakage";
+
+ opp-216000000 {
opp-hz = /bits/ 64 <216000000>;
opp-microvolt = <950000 950000 1350000>;
+ opp-microvolt-L0 = <1050000 1050000 1350000>;
+ opp-microvolt-L1 = <950000 950000 1350000>;
clock-latency-ns = <40000>;
opp-suspend;
};
- opp@408000000 {
+ opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000 950000 1350000>;
+ opp-microvolt-L0 = <1050000 1050000 1350000>;
+ opp-microvolt-L1 = <950000 950000 1350000>;
clock-latency-ns = <40000>;
};
- opp@600000000 {
+ opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000 950000 1350000>;
+ opp-microvolt-L0 = <1050000 1050000 1350000>;
+ opp-microvolt-L1 = <950000 950000 1350000>;
clock-latency-ns = <40000>;
};
- opp@816000000 {
+ opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1025000 1025000 1350000>;
+ opp-microvolt-L0 = <1125000 1125000 1350000>;
+ opp-microvolt-L1 = <1025000 1025000 1350000>;
clock-latency-ns = <40000>;
};
- opp@1008000000 {
+ opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1125000 1125000 1350000>;
+ opp-microvolt-L0 = <1225000 1225000 1350000>;
+ opp-microvolt-L1 = <1125000 1125000 1350000>;
clock-latency-ns = <40000>;
};
- opp@1200000000 {
+ opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1225000 1225000 1350000>;
+ opp-microvolt-L0 = <1325000 1325000 1350000>;
+ opp-microvolt-L1 = <1225000 1225000 1350000>;
clock-latency-ns = <40000>;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
-
- opp@216000000 {
+ leakage-scaling-sel = <
+ 1 24 36
+ 25 254 0
+ >;
+ clocks = <&cru PLL_APLLB>;
+ leakage-voltage-sel = <
+ 1 24 0
+ 25 254 1
+ >;
+ nvmem-cells = <&cpu_leakage>;
+ nvmem-cell-names = "cpu_leakage";
+
+ opp-216000000 {
opp-hz = /bits/ 64 <216000000>;
opp-microvolt = <950000 950000 1350000>;
+ opp-microvolt-L0 = <1050000 1050000 1350000>;
+ opp-microvolt-L1 = <950000 950000 1350000>;
clock-latency-ns = <40000>;
opp-suspend;
};
- opp@408000000 {
+ opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000 950000 1350000>;
+ opp-microvolt-L0 = <1050000 1050000 1350000>;
+ opp-microvolt-L1 = <950000 950000 1350000>;
clock-latency-ns = <40000>;
};
- opp@600000000 {
+ opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000 950000 1350000>;
+ opp-microvolt-L0 = <1050000 1050000 1350000>;
+ opp-microvolt-L1 = <950000 950000 1350000>;
clock-latency-ns = <40000>;
};
- opp@816000000 {
+ opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <975000 975000 1350000>;
+ opp-microvolt-L0 = <1075000 1075000 1350000>;
+ opp-microvolt-L1 = <975000 975000 1350000>;
clock-latency-ns = <40000>;
};
- opp@1008000000 {
+ opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1050000 1050000 1350000>;
+ opp-microvolt-L0 = <1150000 1150000 1350000>;
+ opp-microvolt-L1 = <1050000 1050000 1350000>;
clock-latency-ns = <40000>;
};
- opp@1200000000 {
+ opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1150000 1150000 1350000>;
+ opp-microvolt-L0 = <1250000 1250000 1350000>;
+ opp-microvolt-L1 = <1150000 1150000 1350000>;
clock-latency-ns = <40000>;
};
- opp@1296000000 {
+ opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1225000 1225000 1350000>;
+ opp-microvolt-L0 = <1350000 1350000 1350000>;
+ opp-microvolt-L1 = <1225000 1225000 1350000>;
clock-latency-ns = <40000>;
};
- opp@1416000000 {
+ opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1300000 1300000 1350000>;
+ opp-microvolt-L0 = <1350000 1350000 1350000>;
+ opp-microvolt-L1 = <1300000 1300000 1350000>;
clock-latency-ns = <40000>;
};
- opp@1512000000 {
+ opp-1512000000 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <1350000 1350000 1350000>;
+ opp-microvolt-L0 = <1350000 1350000 1350000>;
+ opp-microvolt-L1 = <1350000 1350000 1350000>;
clock-latency-ns = <40000>;
};
};
};
};
- cpu_avs: cpu-avs {
- cluster0-avs {
- cluster-id = <0>;
- min-volt = <950000>; /* uV */
- min-freq = <216000>; /* KHz */
- leakage-adjust-volt = <
- /* mA mA uV */
- 0 254 0
- >;
- nvmem-cells = <&cpu_leakage>;
- nvmem-cell-names = "cpu_leakage";
- };
- cluster1-avs {
- cluster-id = <1>;
- min-volt = <950000>; /* uV */
- min-freq = <216000>; /* KHz */
- leakage-adjust-volt = <
- /* mA mA uV */
- 0 254 0
- >;
- nvmem-cells = <&cpu_leakage>;
- nvmem-cell-names = "cpu_leakage";
- };
- };
-
arm-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
status = "disabled";
};
};
+
+ dfi: dfi {
+ compatible = "rockchip,rk3368-dfi";
+ status = "disabled";
+ };
+ };
+
+ dmc: dmc {
+ compatible = "rockchip,rk3368-dmc";
+ devfreq-events = <&dfi>;
+ clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_DDRPHY>,
+ <&cru PCLK_DDRUPCTL>;
+ clock-names = "dmc_clk", "pclk_phy", "pclk_upctl";
+ ddr_timing = <&ddr_timing>;
+ upthreshold = <50>;
+ downdifferential = <20>;
+ operating-points-v2 = <&dmc_opp_table>;
+ vop-dclk-mode = <0>;
+ system-status-freq = <
+ /*system status freq(KHz)*/
+ SYS_STATUS_NORMAL 600000
+ SYS_STATUS_REBOOT 600000
+ SYS_STATUS_SUSPEND 192000
+ SYS_STATUS_VIDEO_1080P 300000
+ SYS_STATUS_VIDEO_4K 600000
+ SYS_STATUS_PERFORMANCE 600000
+ SYS_STATUS_BOOST 396000
+ SYS_STATUS_DUALVIEW 600000
+ SYS_STATUS_ISP 528000
+ >;
+ auto-min-freq = <396000>;
+ auto-freq-en = <0>;
+ status = "disabled";
+ };
+
+ dmc_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+
+ opp-192000000 {
+ opp-hz = /bits/ 64 <192000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp-396000000 {
+ opp-hz = /bits/ 64 <396000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp-528000000 {
+ opp-hz = /bits/ 64 <528000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1100000>;
+ };
};
wdt: watchdog@ff800000 {
vop: vop@ff930000 {
compatible = "rockchip,rk3368-vop";
- reg = <0x0 0xff930000 0x0 0x2fc>;
+ reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>;
+ reg-names = "regs", "gamma_lut";
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
#address-cells = <1>;
#size-cells = <0>;
- vop_out_mipi: endpoint@0 {
+ vop_out_dsi: endpoint@0 {
reg = <0>;
- remote-endpoint = <&mipi_in_vop>;
+ remote-endpoint = <&dsi_in_vop>;
};
vop_out_edp: endpoint@1 {
reg = <1>;
remote-endpoint = <&edp_in_vop>;
};
+
+ vop_out_hdmi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&hdmi_in_vop>;
+ };
+
+ vop_out_lvds: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&lvds_in_vop>;
+ };
};
};
status = "disabled";
};
- mipi_dsi_host: mipi-dsi-host@ff960000 {
+ dsi: dsi@ff960000 {
compatible = "rockchip,rk3368-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x4000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_MIPI_DSI0>;
- clock-names = "pclk";
+ clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>;
+ clock-names = "pclk", "hs_clk";
resets = <&cru SRST_MIPIDSI0>;
reset-names = "apb";
phys = <&mipi_dphy>;
ports {
port {
- mipi_in_vop: endpoint {
- remote-endpoint = <&vop_out_mipi>;
+ dsi_in_vop: endpoint {
+ remote-endpoint = <&vop_out_dsi>;
};
};
};
mipi_dphy: mipi-dphy@ff968000 {
compatible = "rockchip,rk3368-mipi-dphy";
reg = <0x0 0xff968000 0x0 0x4000>;
- #phy-cells = <0>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
clock-names = "ref", "pclk";
+ clock-output-names = "mipi_dphy_pll";
+ #clock-cells = <0>;
resets = <&cru SRST_MIPIDPHYTX>;
reset-names = "apb";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ lvds: lvds@ff968000 {
+ compatible = "rockchip,rk3368-lvds";
+ reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff960000 0x0 0x100>;
+ reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
+ clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
+ clock-names = "pclk_lvds", "pclk_lvds_ctl";
+ power-domains = <&power RK3368_PD_VIO>;
+ rockchip,grf = <&grf>;
+ pinctrl-names = "lcdc", "gpio";
+ pinctrl-0 = <&lcdc_lcdc>;
+ pinctrl-1 = <&lcdc_gpio>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lvds_in: port@0 {
+ reg = <0>;
+ lvds_in_vop: endpoint {
+ remote-endpoint = <&vop_out_lvds>;
+ };
+ };
+ };
};
edp: edp@ff970000 {
};
};
+ hdmi: hdmi@ff980000 {
+ compatible = "rockchip,rk3368-dw-hdmi";
+ reg = <0x0 0xff980000 0x0 0x20000>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
+ clock-names = "iahb", "isfr", "cec";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>;
+ resets = <&cru SRST_HDMI>;
+ reset-names = "hdmi";
+ power-domains = <&power RK3368_PD_VIO>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ port {
+ hdmi_in_vop: endpoint {
+ remote-endpoint = <&vop_out_hdmi>;
+ };
+ };
+ };
+ };
+
hevc_mmu: iommu@ff9a0440 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9a0440 0x0 0x40>,
compatible = "operating-points-v2";
opp-shared;
- opp@200000000 {
+ opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1100000>;
};
- opp@288000000 {
+ opp-288000000 {
opp-hz = /bits/ 64 <288000000>;
opp-microvolt = <1100000>;
};
- opp@400000000 {
+ opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1100000>;
};
- opp@576000000 {
+ opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-microvolt = <1200000>;
};
};
};
+ hdmi {
+ hdmi_cec: hdmi-cec {
+ rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ hdmi_i2c_xfer: hdmi-i2c-xfer {
+ rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
+ <3 27 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
pwm3 {
pwm3_pin: pwm3-pin {
- rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
+ rockchip,pins = <3 30 RK_FUNC_3 &pcfg_pull_none>;
};
};
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
- <3 30 RK_FUNC_3 &pcfg_pull_none>;
+ <3 30 RK_FUNC_2 &pcfg_pull_none>;
};
uart3_cts: uart3-cts {
rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
};
};
+
+ lcdc {
+ lcdc_lcdc: lcdc-lcdc {
+ rockchip,pins =
+ <0 14 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
+ <0 15 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
+ <0 16 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
+ <0 17 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
+ <0 18 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
+ <0 19 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
+ <0 20 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
+ <0 21 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
+ <0 22 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
+ <0 23 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
+ <0 24 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
+ <0 25 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
+ <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
+ <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
+ <0 31 RK_FUNC_1 &pcfg_pull_none>, /* DCLK */
+ <0 30 RK_FUNC_1 &pcfg_pull_none>, /* DEN */
+ <0 28 RK_FUNC_1 &pcfg_pull_none>, /* HSYNC */
+ <0 29 RK_FUNC_1 &pcfg_pull_none>; /* VSYN */
+ };
+
+ lcdc_gpio: lcdc-gpio {
+ rockchip,pins =
+ <0 14 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
+ <0 15 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
+ <0 16 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
+ <0 17 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
+ <0 18 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
+ <0 19 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
+ <0 20 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
+ <0 21 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
+ <0 22 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
+ <0 23 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
+ <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
+ <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
+ <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
+ <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
+ <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* DCLK */
+ <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
+ <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
+ <0 29 RK_FUNC_GPIO &pcfg_pull_none>; /* VSYN */
+ };
+ };
+ };
+
+ rockchip_suspend: rockchip-suspend {
+ compatible = "rockchip,pm-rk3368";
+ status = "disabled";
+ rockchip,sleep-debug-en = <0>;
+ rockchip,sleep-mode-config = <
+ (0
+ | RKPM_SLP_ARMOFF_LOGPD
+ | RKPM_SLP_PMU_PLLS_PWRDN
+ | RKPM_SLP_PMU_PMUALIVE_32K
+ | RKPM_SLP_SFT_PLLS_DEEP
+ | RKPM_SLP_PMU_DIS_OSC
+ | RKPM_SLP_SFT_PD_NBSCUS
+ )
+ >;
+ rockchip,wakeup-config = <
+ (0
+ | RKPM_GPIO_WKUP_EN
+ | RKPM_USB_WKUP_EN
+ )
+ >;
};
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff