#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3399-power.h>
-#include <dt-bindings/soc/rockchip_boot-mode.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
#include "rk3399-dram-default-timing.dtsi"
dynamic-power-coefficient = <100>;
clocks = <&cru ARMCLKL>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
- operating-points-v2 = <&cluster0_opp>;
- sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
cpu_l1: cpu@1 {
enable-method = "psci";
clocks = <&cru ARMCLKL>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
- operating-points-v2 = <&cluster0_opp>;
- sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
cpu_l2: cpu@2 {
enable-method = "psci";
clocks = <&cru ARMCLKL>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
- operating-points-v2 = <&cluster0_opp>;
- sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
cpu_l3: cpu@3 {
enable-method = "psci";
clocks = <&cru ARMCLKL>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
- operating-points-v2 = <&cluster0_opp>;
- sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
};
cpu_b0: cpu@100 {
dynamic-power-coefficient = <436>;
clocks = <&cru ARMCLKB>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
- operating-points-v2 = <&cluster1_opp>;
- sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
};
cpu_b1: cpu@101 {
enable-method = "psci";
clocks = <&cru ARMCLKB>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
- operating-points-v2 = <&cluster1_opp>;
- sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
};
idle-states {
min-residency-us = <2000>;
};
};
-
- /include/ "rk3399-sched-energy.dtsi"
-
- };
-
- cluster0_opp: opp_table0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp@408000000 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <800000>;
- clock-latency-ns = <40000>;
- };
- opp@600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <800000>;
- };
- opp@816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <800000>;
- };
- opp@1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <875000>;
- };
- opp@1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <925000>;
- };
- opp@1416000000 {
- opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <1025000>;
- };
- };
-
- cluster1_opp: opp_table1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp@408000000 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <800000>;
- clock-latency-ns = <40000>;
- };
- opp@600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <800000>;
- };
- opp@816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <800000>;
- };
- opp@1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <850000>;
- };
- opp@1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <925000>;
- };
};
cpu_avs: cpu-avs {
};
};
+ cdn_dp: dp@fec00000 {
+ compatible = "rockchip,rk3399-cdn-dp";
+ reg = <0x0 0xfec00000 0x0 0x100000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
+ <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+ clock-names = "core-clk", "pclk", "spdif", "grf";
+ assigned-clocks = <&cru SCLK_DP_CORE>;
+ assigned-clock-rates = <100000000>;
+ power-domains = <&power RK3399_PD_HDCP>;
+ phys = <&tcphy0_dp>, <&tcphy1_dp>;
+ resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
+ <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
+ reset-names = "spdif", "dptx", "apb", "core";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dp_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_dp>;
+ };
+
+ dp_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_dp>;
+ };
+ };
+ };
+ };
+
gic: interrupt-controller@fee00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
status = "disabled";
};
};
pd_gmac@RK3399_PD_GMAC {
reg = <RK3399_PD_GMAC>;
- clocks = <&cru ACLK_GMAC>;
+ clocks = <&cru ACLK_GMAC>,
+ <&cru PCLK_GMAC>;
pm_qos = <&qos_gmac>;
};
pd_perihp@RK3399_PD_PERIHP {
pm_qos = <&qos_isp1_m0>,
<&qos_isp1_m1>;
};
+ pd_tcpc0@RK3399_PD_TCPC0 {
+ reg = <RK3399_PD_TCPD0>;
+ clocks = <&cru SCLK_UPHY0_TCPDCORE>,
+ <&cru SCLK_UPHY0_TCPDPHY_REF>;
+ };
+ pd_tcpc1@RK3399_PD_TCPC1 {
+ reg = <RK3399_PD_TCPD1>;
+ clocks = <&cru SCLK_UPHY1_TCPDCORE>,
+ <&cru SCLK_UPHY1_TCPDPHY_REF>;
+ };
pd_vo@RK3399_PD_VO {
reg = <RK3399_PD_VO>;
#address-cells = <1>;
compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff320000 0x0 0x1000>;
+ pmu_io_domains: pmu-io-domains {
+ compatible = "rockchip,rk3399-pmu-io-voltage-domain";
+ status = "disabled";
+ };
+
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x300>;
- mode-bootloader = <BOOT_LOADER>;
+ mode-bootloader = <BOOT_BL_DOWNLOAD>;
mode-charge = <BOOT_CHARGING>;
mode-fastboot = <BOOT_FASTBOOT>;
- mode-loader = <BOOT_LOADER>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-ums = <BOOT_UMS>;
};
+
+ pmu_pvtm: pmu-pvtm {
+ compatible = "rockchip,rk3399-pmu-pvtm";
+ clocks = <&pmucru SCLK_PVTM_PMU>;
+ clock-names = "pmu";
+ status = "disabled";
+ };
};
spi3: spi@ff350000 {
clock-names = "aclk", "aclk-perf",
"hclk", "pm";
bus-range = <0x0 0x1>;
+ max-link-speed = <1>;
msi-map = <0x0 &its 0x0 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
<0x0 0xfd000000 0x0 0x1000000>;
reg-names = "axi-base", "apb-base";
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
- <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
- reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
+ <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
+ <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
+ <&cru SRST_A_PCIE>;
+ reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
+ "pm", "pclk", "aclk";
status = "disabled";
pcie0_intc: interrupt-controller {
interrupt-controller;
clocks = <&cru SCLK_DDRCLK>;
clock-names = "dmc_clk";
ddr_timing = <&ddr_timing>;
- operating-points-v2 = <&dmc_opp_table>;
status = "disabled";
};
- dmc_opp_table: dmc_opp_table {
- compatible = "operating-points-v2";
+ vpu: vpu_service@ff650000 {
+ compatible = "rockchip,vpu_service";
+ rockchip,grf = <&grf>;
+ iommus = <&vpu_mmu>;
+ iommu_enabled = <1>;
+ reg = <0x0 0xff650000 0x0 0x800>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "irq_dec", "irq_enc";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
+ reset-names = "video_h", "video_a";
+ power-domains = <&power RK3399_PD_VCODEC>;
+ name = "vpu_service";
+ dev_mode = <0>;
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ status = "disabled";
+ };
- opp00 {
- opp-hz = /bits/ 64 <666000000>;
- opp-microvolt = <900000>;
- };
+ vpu_mmu: iommu@ff650800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff650800 0x0 0x40>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vpu_mmu";
+ #iommu-cells = <0>;
+ };
+
+ rkvdec: rkvdec@ff660000 {
+ compatible = "rockchip,rkvdec";
+ rockchip,grf = <&grf>;
+ iommus = <&vdec_mmu>;
+ iommu_enabled = <1>;
+ reg = <0x0 0xff660000 0x0 0x400>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
+ <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
+ clock-names = "aclk_vcodec", "hclk_vcodec",
+ "clk_cabac", "clk_core";
+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
+ reset-names = "video_h", "video_a";
+ power-domains = <&power RK3399_PD_VDU>;
+ dev_mode = <2>;
+ name = "rkvdec";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ status = "disabled";
+ };
+
+ vdec_mmu: iommu@ff660480 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vdec_mmu";
+ #iommu-cells = <0>;
};
rga: rga@ff680000 {
<&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
<&cru ARMCLKL>, <&cru ARMCLKB>,
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
- <&cru PLL_NPLL>,
+ <&cru ACLK_GPU>, <&cru PLL_NPLL>,
<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<400000000>, <200000000>,
<816000000>, <816000000>,
<594000000>, <800000000>,
- <1000000000>,
+ <200000000>, <1000000000>,
<150000000>, <75000000>,
<37500000>,
<100000000>, <100000000>,
#address-cells = <1>;
#size-cells = <1>;
+ io_domains: io-domains {
+ compatible = "rockchip,rk3399-io-voltage-domain";
+ status = "disabled";
+ };
+
emmc_phy: phy@f780 {
compatible = "rockchip,rk3399-emmc-phy";
reg = <0xf780 0x24>;
status = "disabled";
};
};
+
+ pvtm: pvtm {
+ compatible = "rockchip,rk3399-pvtm";
+ clocks = <&cru SCLK_PVTM_CORE_L>,
+ <&cru SCLK_PVTM_CORE_B>,
+ <&cru SCLK_PVTM_GPU>,
+ <&cru SCLK_PVTM_DDR>;
+ clock-names = "core_l", "core_b", "gpu", "ddr";
+ status = "disabled";
+ };
};
tcphy0: phy@ff7c0000 {
clock-names = "tcpdcore", "tcpdphy-ref";
assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
assigned-clock-rates = <50000000>;
+ power-domains = <&power RK3399_PD_TCPD0>;
resets = <&cru SRST_UPHY0>,
<&cru SRST_UPHY0_PIPE_L00>,
<&cru SRST_P_UPHY0_TCPHY>;
clock-names = "tcpdcore", "tcpdphy-ref";
assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
assigned-clock-rates = <50000000>;
+ power-domains = <&power RK3399_PD_TCPD1>;
resets = <&cru SRST_UPHY1>,
<&cru SRST_UPHY1_PIPE_L00>,
<&cru SRST_P_UPHY1_TCPHY>;
clocks = <&cru ACLK_GPU>;
clock-names = "clk_mali";
#cooling-cells = <2>; /* min followed by max */
- operating-points-v2 = <&gpu_opp_table>;
power-domains = <&power RK3399_PD_GPU>;
power-off-delay-ms = <200>;
status = "disabled";
};
};
- gpu_opp_table: gpu_opp_table {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp@200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <900000>;
- };
- opp@300000000 {
- opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <900000>;
- };
- opp@400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <900000>;
- };
-
- };
-
vopl: vop@ff8f0000 {
compatible = "rockchip,rk3399-vop-lit";
reg = <0x0 0xff8f0000 0x0 0x3efc>;
reg = <2>;
remote-endpoint = <&hdmi_in_vopl>;
};
+
+ vopl_out_dp: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&dp_in_vopl>;
+ };
};
};
reg = <2>;
remote-endpoint = <&hdmi_in_vopb>;
};
+
+ vopb_out_dp: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&dp_in_vopb>;
+ };
};
};
status = "disabled";
};
+ isp0_mmu: iommu@ff914000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "isp0_mmu";
+ #iommu-cells = <0>;
+ rk_iommu,disable_reset_quirk;
+ status = "disabled";
+ };
+
+ isp1_mmu: iommu@ff924000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "isp1_mmu";
+ #iommu-cells = <0>;
+ rk_iommu,disable_reset_quirk;
+ status = "disabled";
+ };
+
hdmi: hdmi@ff940000 {
compatible = "rockchip,rk3399-dw-hdmi";
reg = <0x0 0xff940000 0x0 0x20000>;