arm64: dts: rockchip: move vpu/rkvdec to rk3399.dtsi

[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3399.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 9ab8cad27debac386a892d5b14e1764b0ae4190d..4c56705547bcb7c8c89aef97d069395c0e3401a7 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -46,7 +46,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/power/rk3399-power.h>
-#include <dt-bindings/soc/rockchip_boot-mode.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
 #include <dt-bindings/thermal/thermal.h>
 
 #include "rk3399-dram-default-timing.dtsi"
@@ -447,6 +447,46 @@
                };
        };
 
+       cdn_dp: dp@fec00000 {
+               compatible = "rockchip,rk3399-cdn-dp";
+               reg = <0x0 0xfec00000 0x0 0x100000>;
+               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
+                        <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+               clock-names = "core-clk", "pclk", "spdif", "grf";
+               assigned-clocks = <&cru SCLK_DP_CORE>;
+               assigned-clock-rates = <100000000>;
+               power-domains = <&power RK3399_PD_HDCP>;
+               phys = <&tcphy0_dp>, <&tcphy1_dp>;
+               resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
+                        <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
+               reset-names = "spdif", "dptx", "apb", "core";
+               rockchip,grf = <&grf>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               #sound-dai-cells = <1>;
+               status = "disabled";
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       dp_in: port {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               dp_in_vopb: endpoint@0 {
+                                       reg = <0>;
+                                       remote-endpoint = <&vopb_out_dp>;
+                               };
+
+                               dp_in_vopl: endpoint@1 {
+                                       reg = <1>;
+                                       remote-endpoint = <&vopl_out_dp>;
+                               };
+                       };
+               };
+       };
+
        gic: interrupt-controller@fee00000 {
                compatible = "arm,gic-v3";
                #interrupt-cells = <4>;
@@ -1058,6 +1098,11 @@
                compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
                reg = <0x0 0xff320000 0x0 0x1000>;
 
+               pmu_io_domains: pmu-io-domains {
+                       compatible = "rockchip,rk3399-pmu-io-voltage-domain";
+                       status = "disabled";
+               };
+
                reboot-mode {
                        compatible = "syscon-reboot-mode";
                        offset = <0x300>;
@@ -1150,6 +1195,7 @@
                clock-names = "aclk", "aclk-perf",
                              "hclk", "pm";
                bus-range = <0x0 0x1>;
+               max-link-speed = <1>;
                msi-map = <0x0 &its 0x0 0x1000>;
                interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
                             <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
@@ -1245,6 +1291,65 @@
                status = "disabled";
        };
 
+       vpu: vpu_service@ff650000 {
+               compatible = "rockchip,vpu_service";
+               rockchip,grf = <&grf>;
+               iommus = <&vpu_mmu>;
+               iommu_enabled = <1>;
+               reg = <0x0 0xff650000 0x0 0x800>;
+               interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
+                            <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
+               interrupt-names = "irq_dec", "irq_enc";
+               clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+               clock-names = "aclk_vcodec", "hclk_vcodec";
+               resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
+               reset-names = "video_h", "video_a";
+               power-domains = <&power RK3399_PD_VCODEC>;
+               name = "vpu_service";
+               dev_mode = <0>;
+               /* 0 means ion, 1 means drm */
+               allocator = <1>;
+               status = "disabled";
+       };
+
+       vpu_mmu: iommu@ff650800 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff650800 0x0 0x40>;
+               interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
+               interrupt-names = "vpu_mmu";
+               #iommu-cells = <0>;
+       };
+
+       rkvdec: rkvdec@ff660000 {
+               compatible = "rockchip,rkvdec";
+               rockchip,grf = <&grf>;
+               iommus = <&vdec_mmu>;
+               iommu_enabled = <1>;
+               reg = <0x0 0xff660000 0x0 0x400>;
+               interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
+               interrupt-names = "irq_dec";
+               clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
+                        <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
+               clock-names = "aclk_vcodec", "hclk_vcodec",
+                             "clk_cabac", "clk_core";
+               resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
+               reset-names = "video_h", "video_a";
+               power-domains = <&power RK3399_PD_VDU>;
+               dev_mode = <2>;
+               name = "rkvdec";
+               /* 0 means ion, 1 means drm */
+               allocator = <1>;
+               status = "disabled";
+       };
+
+       vdec_mmu: iommu@ff660480 {
+               compatible = "rockchip,iommu";
+               reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
+               interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
+               interrupt-names = "vdec_mmu";
+               #iommu-cells = <0>;
+       };
+
        rga: rga@ff680000 {
                compatible = "rockchip,rk3399-rga";
                reg = <0x0 0xff680000 0x0 0x10000>;
@@ -1331,6 +1436,11 @@
                #address-cells = <1>;
                #size-cells = <1>;
 
+               io_domains: io-domains {
+                       compatible = "rockchip,rk3399-io-voltage-domain";
+                       status = "disabled";
+               };
+
                emmc_phy: phy@f780 {
                        compatible = "rockchip,rk3399-emmc-phy";
                        reg = <0xf780 0x24>;
@@ -1602,6 +1712,11 @@
                                reg = <2>;
                                remote-endpoint = <&hdmi_in_vopl>;
                        };
+
+                       vopl_out_dp: endpoint@3 {
+                               reg = <3>;
+                               remote-endpoint = <&dp_in_vopl>;
+                       };
                };
        };
 
@@ -1655,6 +1770,11 @@
                                reg = <2>;
                                remote-endpoint = <&hdmi_in_vopb>;
                        };
+
+                       vopb_out_dp: endpoint@3 {
+                               reg = <3>;
+                               remote-endpoint = <&dp_in_vopb>;
+                       };
                };
        };
 
@@ -1684,6 +1804,7 @@
                interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
                interrupt-names = "isp0_mmu";
                #iommu-cells = <0>;
+               rk_iommu,disable_reset_quirk;
                status = "disabled";
        };
 
@@ -1693,6 +1814,7 @@
                interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
                interrupt-names = "isp1_mmu";
                #iommu-cells = <0>;
+               rk_iommu,disable_reset_quirk;
                status = "disabled";
        };