#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3399-power.h>
-#include <dt-bindings/soc/rockchip_boot-mode.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/suspend/rockchip-rk3399.h>
#include <dt-bindings/thermal/thermal.h>
#include "rk3399-dram-default-timing.dtsi"
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
+ dsi0 = &dsi;
+ dsi1 = &dsi1;
};
cpus {
};
};
- cpu_avs: cpu-avs {
- cluster0-avs {
- cluster-id = <0>;
- min-volt = <800000>; /* uV */
- min-freq = <408000>; /* KHz */
- leakage-adjust-volt = <
- /* mA mA uV */
- 0 254 0
- >;
- nvmem-cells = <&cpul_leakage>;
- nvmem-cell-names = "cpu_leakage";
- };
- cluster1-avs {
- cluster-id = <1>;
- min-volt = <800000>; /* uV */
- min-freq = <408000>; /* KHz */
- leakage-adjust-volt = <
- /* mA mA uV */
- 0 254 0
- >;
- nvmem-cells = <&cpub_leakage>;
- nvmem-cell-names = "cpu_leakage";
- };
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
+ };
+
+ pmu_a72 {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
};
timer {
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
};
- pmu_a53 {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
};
- pmu_a72 {
- compatible = "arm,cortex-a72-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
+ dummy_cpll: dummy_cpll {
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "dummy_cpll";
+ #clock-cells = <0>;
};
- xin24m: xin24m {
+ dummy_vpll: dummy_vpll {
compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "dummy_vpll";
#clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
};
amba {
};
};
- gmac: eth@fe300000 {
+ gmac: ethernet@fe300000 {
compatible = "rockchip,rk3399-gmac";
reg = <0x0 0xfe300000 0x0 0x10000>;
rockchip,grf = <&grf>;
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
+ snps,tx-ipgap-linecheck-dis-quirk;
snps,xhci-slow-suspend-quirk;
+ snps,usb3-warm-reset-on-resume-quirk;
status = "disabled";
};
};
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
+ snps,tx-ipgap-linecheck-dis-quirk;
snps,xhci-slow-suspend-quirk;
+ snps,usb3-warm-reset-on-resume-quirk;
status = "disabled";
};
};
+ cdn_dp: dp@fec00000 {
+ compatible = "rockchip,rk3399-cdn-dp";
+ reg = <0x0 0xfec00000 0x0 0x100000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
+ <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+ clock-names = "core-clk", "pclk", "spdif", "grf";
+ assigned-clocks = <&cru SCLK_DP_CORE>;
+ assigned-clock-rates = <100000000>;
+ power-domains = <&power RK3399_PD_HDCP>;
+ phys = <&tcphy0_dp>, <&tcphy1_dp>;
+ resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
+ <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
+ reset-names = "spdif", "dptx", "apb", "core";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #sound-dai-cells = <1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dp_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dp_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_dp>;
+ };
+
+ dp_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_dp>;
+ };
+ };
+ };
+ };
+
gic: interrupt-controller@fee00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <4>;
};
ppi-partitions {
- part0: interrupt-partition-0 {
+ ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
};
- part1: interrupt-partition-1 {
+ ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu_b0 &cpu_b1>;
};
};
status = "disabled";
};
- thermal-zones {
+ thermal_zones: thermal-zones {
soc_thermal: soc-thermal {
polling-delay-passive = <20>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
pmugrf: syscon@ff320000 {
compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff320000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pmu_io_domains: io-domains {
+ compatible = "rockchip,rk3399-pmu-io-voltage-domain";
+ status = "disabled";
+ };
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x300>;
- mode-bootloader = <BOOT_LOADER>;
+ mode-bootloader = <BOOT_BL_DOWNLOAD>;
mode-charge = <BOOT_CHARGING>;
mode-fastboot = <BOOT_FASTBOOT>;
- mode-loader = <BOOT_LOADER>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-ums = <BOOT_UMS>;
compatible = "rockchip,rk3399-pcie";
#address-cells = <3>;
#size-cells = <2>;
+ aspm-no-l0s;
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
clock-names = "aclk", "aclk-perf",
"hclk", "pm";
bus-range = <0x0 0x1>;
+ max-link-speed = <1>;
+ linux,pci-domain = <0>;
msi-map = <0x0 &its 0x0 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
status = "disabled";
};
+ vpu: vpu_service@ff650000 {
+ compatible = "rockchip,vpu_service";
+ rockchip,grf = <&grf>;
+ iommus = <&vpu_mmu>;
+ iommu_enabled = <1>;
+ reg = <0x0 0xff650000 0x0 0x800>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "irq_dec", "irq_enc";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
+ reset-names = "video_h", "video_a";
+ power-domains = <&power RK3399_PD_VCODEC>;
+ name = "vpu_service";
+ dev_mode = <0>;
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ status = "disabled";
+ };
+
+ vpu_mmu: iommu@ff650800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff650800 0x0 0x40>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vpu_mmu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3399_PD_VCODEC>;
+ #iommu-cells = <0>;
+ };
+
+ rkvdec: rkvdec@ff660000 {
+ compatible = "rockchip,rkvdec";
+ rockchip,grf = <&grf>;
+ iommus = <&vdec_mmu>;
+ iommu_enabled = <1>;
+ reg = <0x0 0xff660000 0x0 0x400>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
+ <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
+ clock-names = "aclk_vcodec", "hclk_vcodec",
+ "clk_cabac", "clk_core";
+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>,
+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>,
+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>;
+ reset-names = "video_h", "video_a", "video_core", "video_cabac",
+ "niu_a", "niu_h";
+ power-domains = <&power RK3399_PD_VDU>;
+ dev_mode = <2>;
+ name = "rkvdec";
+ /* 0 means ion, 1 means drm */
+ allocator = <1>;
+ status = "disabled";
+ };
+
+ vdec_mmu: iommu@ff660480 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vdec_mmu";
+ clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3399_PD_VDU>;
+ #iommu-cells = <0>;
+ };
+
+ iep: iep@ff670000 {
+ compatible = "rockchip,iep";
+ iommu_enabled = <1>;
+ iommus = <&iep_mmu>;
+ reg = <0x0 0xff670000 0x0 0x800>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk_iep", "hclk_iep";
+ power-domains = <&power RK3399_PD_IEP>;
+ allocator = <1>;
+ version = <2>;
+ status = "disabled";
+ };
+
+ iep_mmu: iommu@ff670800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff670800 0x0 0x40>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep_mmu";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
rga: rga@ff680000 {
compatible = "rockchip,rk3399-rga";
reg = <0x0 0xff680000 0x0 0x10000>;
clock-names = "pclk_efuse";
/* Data cells */
+ efuse_id: id {
+ reg = <0x07 0x10>;
+ };
cpul_leakage: cpul-leakage {
reg = <0x1a 0x1>;
};
#address-cells = <1>;
#size-cells = <1>;
+ io_domains: io-domains {
+ compatible = "rockchip,rk3399-io-voltage-domain";
+ status = "disabled";
+ };
+
emmc_phy: phy@f780 {
compatible = "rockchip,rk3399-emmc-phy";
reg = <0xf780 0x24>;
vopl: vop@ff8f0000 {
compatible = "rockchip,rk3399-vop-lit";
- reg = <0x0 0xff8f0000 0x0 0x3efc>;
+ reg = <0x0 0xff8f0000 0x0 0x600>,
+ <0x0 0xff8f1c00 0x0 0x200>,
+ <0x0 0xff8f2000 0x0 0x400>;
+ reg-names = "regs", "cabc_lut", "gamma_lut";
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
- clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>, <&cru DCLK_VOP1_DIV>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
reset-names = "axi", "ahb", "dclk";
power-domains = <&power RK3399_PD_VOPL>;
#address-cells = <1>;
#size-cells = <0>;
- vopl_out_mipi: endpoint@0 {
+ vopl_out_dsi: endpoint@0 {
reg = <0>;
- remote-endpoint = <&mipi_in_vopl>;
+ remote-endpoint = <&dsi_in_vopl>;
};
vopl_out_edp: endpoint@1 {
reg = <2>;
remote-endpoint = <&hdmi_in_vopl>;
};
+
+ vopl_out_dp: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&dp_in_vopl>;
+ };
+
+ vopl_out_dsi1: endpoint@4 {
+ reg = <4>;
+ remote-endpoint = <&dsi1_in_vopl>;
+ };
};
};
reg = <0x0 0xff8f3f00 0x0 0x100>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopl_mmu";
+ clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3399_PD_VOPL>;
#iommu-cells = <0>;
status = "disabled";
};
vopb: vop@ff900000 {
compatible = "rockchip,rk3399-vop-big";
- reg = <0x0 0xff900000 0x0 0x3efc>;
+ reg = <0x0 0xff900000 0x0 0x600>,
+ <0x0 0xff901c00 0x0 0x200>,
+ <0x0 0xff902000 0x0 0x1000>;
+ reg-names = "regs", "cabc_lut", "gamma_lut";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
- clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>, <&cru DCLK_VOP0_DIV>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source";
resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
reset-names = "axi", "ahb", "dclk";
power-domains = <&power RK3399_PD_VOPB>;
remote-endpoint = <&edp_in_vopb>;
};
- vopb_out_mipi: endpoint@1 {
+ vopb_out_dsi: endpoint@1 {
reg = <1>;
- remote-endpoint = <&mipi_in_vopb>;
+ remote-endpoint = <&dsi_in_vopb>;
};
vopb_out_hdmi: endpoint@2 {
reg = <2>;
remote-endpoint = <&hdmi_in_vopb>;
};
+
+ vopb_out_dp: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&dp_in_vopb>;
+ };
+
+ vopb_out_dsi1: endpoint@4 {
+ reg = <4>;
+ remote-endpoint = <&dsi1_in_vopb>;
+ };
};
};
reg = <0x0 0xff903f00 0x0 0x100>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopb_mmu";
+ clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3399_PD_VOPB>;
#iommu-cells = <0>;
status = "disabled";
};
+ isp0_mmu: iommu@ff914000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "isp0_mmu";
+ #iommu-cells = <0>;
+ clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3399_PD_ISP0>;
+ rk_iommu,disable_reset_quirk;
+ status = "disabled";
+ };
+
+ isp1_mmu: iommu@ff924000 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "isp1_mmu";
+ #iommu-cells = <0>;
+ clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3399_PD_ISP1>;
+ rk_iommu,disable_reset_quirk;
+ status = "disabled";
+ };
+
hdmi: hdmi@ff940000 {
compatible = "rockchip,rk3399-dw-hdmi";
reg = <0x0 0xff940000 0x0 0x20000>;
reg-io-width = <4>;
rockchip,grf = <&grf>;
- power-domains = <&power RK3399_PD_HDCP>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_i2c_xfer>;
+ power-domains = <&power RK3399_PD_HDCP>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
+ clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
clock-names = "iahb", "isfr", "vpll", "grf";
status = "disabled";
};
};
- mipi_dsi: mipi@ff960000 {
- compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
+ dsi: dsi@ff960000 {
+ compatible = "rockchip,rk3399-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x8000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
+ clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
<&cru SCLK_DPHY_TX0_CFG>;
clock-names = "ref", "pclk", "phy_cfg";
+ resets = <&cru SRST_P_MIPI_DSI0>;
+ reset-names = "apb";
power-domains = <&power RK3399_PD_VIO>;
rockchip,grf = <&grf>;
#address-cells = <1>;
status = "disabled";
ports {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_dsi>;
+ };
+
+ dsi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_dsi>;
+ };
+ };
+ };
+ };
+
+ dsi1: dsi@ff968000 {
+ compatible = "rockchip,rk3399-mipi-dsi";
+ reg = <0x0 0xff968000 0x0 0x8000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
+ <&cru SCLK_DPHY_TX1RX1_CFG>;
+ clock-names = "ref", "pclk", "phy_cfg";
+ resets = <&cru SRST_P_MIPI_DSI1>;
+ reset-names = "apb";
+ power-domains = <&power RK3399_PD_VIO>;
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
- mipi_in: port {
+ ports {
+ port {
#address-cells = <1>;
#size-cells = <0>;
- mipi_in_vopb: endpoint@0 {
+ dsi1_in_vopb: endpoint@0 {
reg = <0>;
- remote-endpoint = <&vopb_out_mipi>;
+ remote-endpoint = <&vopb_out_dsi1>;
};
- mipi_in_vopl: endpoint@1 {
+
+ dsi1_in_vopl: endpoint@1 {
reg = <1>;
- remote-endpoint = <&vopl_out_mipi>;
+ remote-endpoint = <&vopl_out_dsi1>;
};
};
};
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vopl_out>, <&vopb_out>;
+ clocks = <&cru PLL_VPLL>, <&cru PLL_CPLL>;
+ clock-names = "hdmi-tmds-pll", "default-vop-pll";
status = "disabled";
};
rockchip,pins =
<4 24 RK_FUNC_1 &pcfg_pull_none>;
};
+
+ pcie_clkreqn_cpm: pci-clkreqn-cpm {
+ /*
+ * Since our pcie doesn't support
+ * ClockPM(CPM), we want to hack this as
+ * gpio, so the EP could be able to
+ * de-assert it along and make ClockPM(CPM)
+ * work.
+ */
+ rockchip,pins =
+ <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
+ rockchip,pins =
+ <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
};
};
+
+ rockchip_suspend: rockchip-suspend {
+ compatible = "rockchip,pm-rk3399";
+ status = "disabled";
+ rockchip,sleep-debug-en = <0>;
+ rockchip,virtual-poweroff = <0>;
+ rockchip,sleep-mode-config = <
+ (0
+ | RKPM_SLP_ARMPD
+ | RKPM_SLP_PERILPPD
+ | RKPM_SLP_DDR_RET
+ | RKPM_SLP_PLLPD
+ | RKPM_SLP_OSC_DIS
+ | RKPM_SLP_CENTER_PD
+ | RKPM_SLP_AP_PWROFF
+ )
+ >;
+ rockchip,wakeup-config = <
+ (0
+ | RKPM_GPIO_WKUP_EN
+ )
+ >;
+ };
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff