Blackfin: push gpio (port) defines into common headers

[firefly-linux-kernel-4.4.55.git] / arch / blackfin / mach-bf538 / include / mach / defBF539.h

diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 1dcf16f25b1f215af773061fd2edbf927666f252..e0aad63b55ca07fd69e75756b386108997abe762 100644 (file)
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1627,135 +1627,6 @@
 #define        ERR_TYP_P0              0x0E
 #define        ERR_TYP_P1              0x0F
 
-
-/*/ ******************  GENERAL-PURPOSE I/O  ********************* */
-/*  Flag I/O (FIO_) Masks */
-#define        PF0                     0x0001
-#define        PF1                     0x0002
-#define        PF2                     0x0004
-#define        PF3                     0x0008
-#define        PF4                     0x0010
-#define        PF5                     0x0020
-#define        PF6                     0x0040
-#define        PF7                     0x0080
-#define        PF8                     0x0100
-#define        PF9                     0x0200
-#define        PF10            0x0400
-#define        PF11            0x0800
-#define        PF12            0x1000
-#define        PF13            0x2000
-#define        PF14            0x4000
-#define        PF15            0x8000
-
-/*  PORT F BIT POSITIONS */
-#define        PF0_P           0x0
-#define        PF1_P           0x1
-#define        PF2_P           0x2
-#define        PF3_P           0x3
-#define        PF4_P           0x4
-#define        PF5_P           0x5
-#define        PF6_P           0x6
-#define        PF7_P           0x7
-#define        PF8_P           0x8
-#define        PF9_P           0x9
-#define        PF10_P          0xA
-#define        PF11_P          0xB
-#define        PF12_P          0xC
-#define        PF13_P          0xD
-#define        PF14_P          0xE
-#define        PF15_P          0xF
-
-
-/*******************   GPIO MASKS  *********************/
-/* Port        C Masks */
-#define        PC0             0x0001
-#define        PC1             0x0002
-#define        PC4             0x0010
-#define        PC5             0x0020
-#define        PC6             0x0040
-#define        PC7             0x0080
-#define        PC8             0x0100
-#define        PC9             0x0200
-/* Port        C Bit Positions */
-#define        PC0_P   0x0
-#define        PC1_P   0x1
-#define        PC4_P   0x4
-#define        PC5_P   0x5
-#define        PC6_P   0x6
-#define        PC7_P   0x7
-#define        PC8_P   0x8
-#define        PC9_P   0x9
-
-/* Port        D */
-#define        PD0             0x0001
-#define        PD1             0x0002
-#define        PD2             0x0004
-#define        PD3             0x0008
-#define        PD4             0x0010
-#define        PD5             0x0020
-#define        PD6             0x0040
-#define        PD7             0x0080
-#define        PD8             0x0100
-#define        PD9             0x0200
-#define        PD10    0x0400
-#define        PD11    0x0800
-#define        PD12    0x1000
-#define        PD13    0x2000
-#define        PD14    0x4000
-#define        PD15    0x8000
-/* Port        D Bit Positions */
-#define        PD0_P   0x0
-#define        PD1_P   0x1
-#define        PD2_P   0x2
-#define        PD3_P   0x3
-#define        PD4_P   0x4
-#define        PD5_P   0x5
-#define        PD6_P   0x6
-#define        PD7_P   0x7
-#define        PD8_P   0x8
-#define        PD9_P   0x9
-#define        PD10_P  0xA
-#define        PD11_P  0xB
-#define        PD12_P  0xC
-#define        PD13_P  0xD
-#define        PD14_P  0xE
-#define        PD15_P  0xF
-
-/* Port        E */
-#define        PE0             0x0001
-#define        PE1             0x0002
-#define        PE2             0x0004
-#define        PE3             0x0008
-#define        PE4             0x0010
-#define        PE5             0x0020
-#define        PE6             0x0040
-#define        PE7             0x0080
-#define        PE8             0x0100
-#define        PE9             0x0200
-#define        PE10    0x0400
-#define        PE11    0x0800
-#define        PE12    0x1000
-#define        PE13    0x2000
-#define        PE14    0x4000
-#define        PE15    0x8000
-/* Port        E Bit Positions */
-#define        PE0_P   0x0
-#define        PE1_P   0x1
-#define        PE2_P   0x2
-#define        PE3_P   0x3
-#define        PE4_P   0x4
-#define        PE5_P   0x5
-#define        PE6_P   0x6
-#define        PE7_P   0x7
-#define        PE8_P   0x8
-#define        PE9_P   0x9
-#define        PE10_P  0xA
-#define        PE11_P  0xB
-#define        PE12_P  0xC
-#define        PE13_P  0xD
-#define        PE14_P  0xE
-#define        PE15_P  0xF
-
 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
 /* EBIU_AMGCTL Masks */
 #define        AMCKEN          0x0001  /* Enable CLKOUT */