blackfin: bf60x: Rename the DDR controller macro

[firefly-linux-kernel-4.4.55.git] / arch / blackfin / mach-bf609 / include / mach / cdefBF60x_base.h

diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
index 88a05264ebdad3db949793e8a4d1cd25e34c844a..4954cf3f7e16d82ec9dba7b5bc1841362e465c94 100644 (file)
--- a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
+++ b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
@@ -298,24 +298,24 @@
 #define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
 
 /* DDR2 Memory Control Registers */
-#define bfin_read_DDR0_CFG() bfin_read32(DDR0_CFG)
-#define bfin_write_DDR0_CFG(val) bfin_write32(DDR0_CFG, val)
-#define bfin_read_DDR0_TR0() bfin_read32(DDR0_TR0)
-#define bfin_write_DDR0_TR0(val) bfin_write32(DDR0_TR0, val)
-#define bfin_read_DDR0_TR1() bfin_read32(DDR0_TR1)
-#define bfin_write_DDR0_TR1(val) bfin_write32(DDR0_TR1, val)
-#define bfin_read_DDR0_TR2() bfin_read32(DDR0_TR2)
-#define bfin_write_DDR0_TR2(val) bfin_write32(DDR0_TR2, val)
-#define bfin_read_DDR0_MR() bfin_read32(DDR0_MR)
-#define bfin_write_DDR0_MR(val) bfin_write32(DDR0_MR, val)
-#define bfin_read_DDR0_EMR1() bfin_read32(DDR0_EMR1)
-#define bfin_write_DDR0_EMR1(val) bfin_write32(DDR0_EMR1, val)
-#define bfin_read_DDR0_CTL() bfin_read32(DDR0_CTL)
-#define bfin_write_DDR0_CTL(val) bfin_write32(DDR0_CTL, val)
-#define bfin_read_DDR0_STAT() bfin_read32(DDR0_STAT)
-#define bfin_write_DDR0_STAT(val) bfin_write32(DDR0_STAT, val)
-#define bfin_read_DDR0_DLLCTL() bfin_read32(DDR0_DLLCTL)
-#define bfin_write_DDR0_DLLCTL(val) bfin_write32(DDR0_DLLCTL, val)
+#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
+#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
+#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
+#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
+#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
+#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
+#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
+#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
+#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
+#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
+#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
+#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
+#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
+#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
+#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
+#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
+#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
+#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
 
 /* DDR BankRead and Write Count Registers */