Blackfin: allow cache funcs to be in L1 for IFLUSH Anomaly 05000491

[firefly-linux-kernel-4.4.55.git] / arch / blackfin / mach-common / cache.S

diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index ea540318a228c0b8fc5dfc35da0c695eeea64d02..790c767ca95af8dc82ffc3fc56e7f69c5fb9df81 100644 (file)
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -11,7 +11,11 @@
 #include <asm/cache.h>
 #include <asm/page.h>
 
+#ifdef CONFIG_CACHE_FLUSH_L1
+.section .l1.text
+#else
 .text
+#endif
 
 /* 05000443 - IFLUSH cannot be last instruction in hardware loop */
 #if ANOMALY_05000443
@@ -64,17 +68,6 @@
 
 /* Invalidate all instruction cache lines assocoiated with this memory area */
 ENTRY(_blackfin_icache_flush_range)
-/*
- * Walkaround to avoid loading wrong instruction after invalidating icache
- * and following sequence is met.
- *
- * 1) One instruction address is cached in the instruction cache.
- * 2) This instruction in SDRAM is changed.
- * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
- * 4) This instruction is executed again, but the old one is loaded.
- */
-       P0 = R0;
-       IFLUSH[P0];
        do_flush IFLUSH
 ENDPROC(_blackfin_icache_flush_range)