MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code

[firefly-linux-kernel-4.4.55.git] / arch / mips / kernel / cpu-probe.c

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 3562b854f2cd4e0e61086073e11534d39479484f..f7faa3fb79b242197e1cc2f96d5a874112ff33aa 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -181,12 +181,14 @@ void __init check_wait(void)
        case CPU_5KC:
        case CPU_25KF:
        case CPU_PR4450:
-       case CPU_BCM3302:
-       case CPU_BCM6338:
-       case CPU_BCM6348:
-       case CPU_BCM6358:
+       case CPU_BMIPS3300:
+       case CPU_BMIPS4350:
+       case CPU_BMIPS4380:
+       case CPU_BMIPS5000:
        case CPU_CAVIUM_OCTEON:
        case CPU_CAVIUM_OCTEON_PLUS:
+       case CPU_CAVIUM_OCTEON2:
+       case CPU_JZRISC:
                cpu_wait = r4k_wait;
                break;
 
@@ -760,6 +762,9 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
                ok = decode_config4(c);
 
        mips_probe_watch_registers(c);
+
+       if (cpu_has_mips_r2)
+               c->core = read_c0_ebase() & 0x3ff;
 }
 
 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
@@ -898,33 +903,37 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 {
        decode_configs(c);
        switch (c->processor_id & 0xff00) {
-       case PRID_IMP_BCM3302:
-        /* same as PRID_IMP_BCM6338 */
-               c->cputype = CPU_BCM3302;
-               __cpu_name[cpu] = "Broadcom BCM3302";
-               break;
-       case PRID_IMP_BCM4710:
-               c->cputype = CPU_BCM4710;
-               __cpu_name[cpu] = "Broadcom BCM4710";
-               break;
-       case PRID_IMP_BCM6345:
-               c->cputype = CPU_BCM6345;
-               __cpu_name[cpu] = "Broadcom BCM6345";
+       case PRID_IMP_BMIPS32:
+               c->cputype = CPU_BMIPS32;
+               __cpu_name[cpu] = "Broadcom BMIPS32";
+               break;
+       case PRID_IMP_BMIPS3300:
+       case PRID_IMP_BMIPS3300_ALT:
+       case PRID_IMP_BMIPS3300_BUG:
+               c->cputype = CPU_BMIPS3300;
+               __cpu_name[cpu] = "Broadcom BMIPS3300";
+               break;
+       case PRID_IMP_BMIPS43XX: {
+               int rev = c->processor_id & 0xff;
+
+               if (rev >= PRID_REV_BMIPS4380_LO &&
+                               rev <= PRID_REV_BMIPS4380_HI) {
+                       c->cputype = CPU_BMIPS4380;
+                       __cpu_name[cpu] = "Broadcom BMIPS4380";
+               } else {
+                       c->cputype = CPU_BMIPS4350;
+                       __cpu_name[cpu] = "Broadcom BMIPS4350";
+               }
                break;
-       case PRID_IMP_BCM6348:
-               c->cputype = CPU_BCM6348;
-               __cpu_name[cpu] = "Broadcom BCM6348";
+       }
+       case PRID_IMP_BMIPS5000:
+               c->cputype = CPU_BMIPS5000;
+               __cpu_name[cpu] = "Broadcom BMIPS5000";
+               c->options |= MIPS_CPU_ULRI;
                break;
-       case PRID_IMP_BCM4350:
-               switch (c->processor_id & 0xf0) {
-               case PRID_REV_BCM6358:
-                       c->cputype = CPU_BCM6358;
-                       __cpu_name[cpu] = "Broadcom BCM6358";
-                       break;
-               default:
-                       c->cputype = CPU_UNKNOWN;
-                       break;
-               }
+       case PRID_IMP_BMIPS4KC:
+               c->cputype = CPU_4KC;
+               __cpu_name[cpu] = "MIPS 4Kc";
                break;
        }
 }
@@ -949,6 +958,12 @@ platform:
                if (cpu == 0)
                        __elf_platform = "octeon";
                break;
+       case PRID_IMP_CAVIUM_CN63XX:
+               c->cputype = CPU_CAVIUM_OCTEON2;
+               __cpu_name[cpu] = "Cavium Octeon II";
+               if (cpu == 0)
+                       __elf_platform = "octeon2";
+               break;
        default:
                printk(KERN_INFO "Unknown Octeon chip!\n");
                c->cputype = CPU_UNKNOWN;
@@ -956,6 +971,22 @@ platform:
        }
 }
 
+static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
+{
+       decode_configs(c);
+       /* JZRISC does not implement the CP0 counter. */
+       c->options &= ~MIPS_CPU_COUNTER;
+       switch (c->processor_id & 0xff00) {
+       case PRID_IMP_JZRISC:
+               c->cputype = CPU_JZRISC;
+               __cpu_name[cpu] = "Ingenic JZRISC";
+               break;
+       default:
+               panic("Unknown Ingenic Processor ID!");
+               break;
+       }
+}
+
 const char *__cpu_name[NR_CPUS];
 const char *__elf_platform;
 
@@ -994,6 +1025,9 @@ __cpuinit void cpu_probe(void)
        case PRID_COMP_CAVIUM:
                cpu_probe_cavium(c, cpu);
                break;
+       case PRID_COMP_INGENIC:
+               cpu_probe_ingenic(c, cpu);
+               break;
        }
 
        BUG_ON(!__cpu_name[cpu]);