return NOTIFY_OK;
}
+static int wait_on_fp_mode_switch(atomic_t *p)
+{
+ /*
+ * The FP mode for this task is currently being switched. That may
+ * involve modifications to the format of this tasks FP context which
+ * make it unsafe to proceed with execution for the moment. Instead,
+ * schedule some other task.
+ */
+ schedule();
+ return 0;
+}
+
static int enable_restore_fp_context(int msa)
{
int err, was_fpu_owner, prior_msa;
+ /*
+ * If an FP mode switch is currently underway, wait for it to
+ * complete before proceeding.
+ */
+ wait_on_atomic_t(¤t->mm->context.fp_mode_switching,
+ wait_on_fp_mode_switch, TASK_KILLABLE);
+
if (!used_math()) {
/* First time FP context user. */
preempt_disable();
case CPU_INTERAPTIV:
case CPU_PROAPTIV:
case CPU_P5600:
+ case CPU_QEMU_GENERIC:
{
#define ERRCTL_PE 0x80000000
#define ERRCTL_L2P 0x00800000
printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
reg_val & (1<<30) ? "secondary" : "primary",
reg_val & (1<<31) ? "data" : "insn");
- if (cpu_has_mips_r2 &&
+ if ((cpu_has_mips_r2_r6) &&
((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
reg_val & (1<<29) ? "ED " : "",
unsigned int reg_val;
/* For the moment, report the problem and hang. */
- if (cpu_has_mips_r2 &&
+ if ((cpu_has_mips_r2_r6) &&
((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
read_c0_ecc());
{
unsigned int hwrena = cpu_hwrena_impl_bits;
- if (cpu_has_mips_r2)
+ if (cpu_has_mips_r2_r6)
hwrena |= 0x0000000f;
if (!noulri && cpu_has_userlocal)
* o read IntCtl.IPTI to determine the timer interrupt
* o read IntCtl.IPPCI to determine the performance counter interrupt
*/
- if (cpu_has_mips_r2) {
+ if (cpu_has_mips_r2_r6) {
cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
#else
ebase = CKSEG0;
#endif
- if (cpu_has_mips_r2)
+ if (cpu_has_mips_r2_r6)
ebase += (read_c0_ebase() & 0x3ffff000);
}