Merge branch '81xx' into omap-for-v4.4/fixes

[firefly-linux-kernel-4.4.55.git] / arch / mips / ralink / mt7620.c

diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 4d1a0339dd54c37c3d13866b67e90dbdadd3e5d9..dfb04fcedb042d9b80621ac3197886a1ea3bccda 100644 (file)
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -37,8 +37,11 @@
 #define PMU1_CFG               0x8C
 #define DIG_SW_SEL             BIT(25)
 
-/* is this a MT7620 or a MT7628 */
-enum mt762x_soc_type mt762x_soc;
+/* clock scaling */
+#define CLKCFG_FDIV_MASK       0x1f00
+#define CLKCFG_FDIV_USB_VAL    0x0300
+#define CLKCFG_FFRAC_MASK      0x001f
+#define CLKCFG_FFRAC_USB_VAL   0x0003
 
 /* EFUSE bits */
 #define EFUSE_MT7688           0x100000
@@ -235,8 +238,8 @@ static struct rt2880_pmx_group mt7628an_pinmux_data[] = {
 
 static inline int is_mt76x8(void)
 {
-       return mt762x_soc == MT762X_SOC_MT7628AN ||
-              mt762x_soc == MT762X_SOC_MT7688;
+       return ralink_soc == MT762X_SOC_MT7628AN ||
+              ralink_soc == MT762X_SOC_MT7688;
 }
 
 static __init u32
@@ -435,6 +438,20 @@ void __init ralink_clk_init(void)
        ralink_clk_add("10000b00.spi", sys_rate);
        ralink_clk_add("10000c00.uartlite", periph_rate);
        ralink_clk_add("10180000.wmac", xtal_rate);
+
+       if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
+               /*
+                * When the CPU goes into sleep mode, the BUS clock will be
+                * too low for USB to function properly. Adjust the busses
+                * fractional divider to fix this
+                */
+               u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
+
+               val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
+               val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
+
+               rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
+       }
 }
 
 void __init ralink_of_remap(void)
@@ -511,25 +528,22 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
        if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
                if (bga) {
-                       mt762x_soc = MT762X_SOC_MT7620A;
+                       ralink_soc = MT762X_SOC_MT7620A;
                        name = "MT7620A";
                        soc_info->compatible = "ralink,mt7620a-soc";
                } else {
-                       mt762x_soc = MT762X_SOC_MT7620N;
+                       ralink_soc = MT762X_SOC_MT7620N;
                        name = "MT7620N";
                        soc_info->compatible = "ralink,mt7620n-soc";
-#ifdef CONFIG_PCI
-                       panic("mt7620n is only supported for non pci kernels");
-#endif
                }
        } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
                u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
 
                if (efuse & EFUSE_MT7688) {
-                       mt762x_soc = MT762X_SOC_MT7688;
+                       ralink_soc = MT762X_SOC_MT7688;
                        name = "MT7688";
                } else {
-                       mt762x_soc = MT762X_SOC_MT7628AN;
+                       ralink_soc = MT762X_SOC_MT7628AN;
                        name = "MT7628AN";
                }
                soc_info->compatible = "ralink,mt7628an-soc";