powerpc/booke64: Use SPRG0/3 scratch for bolted TLB miss & crit int

[firefly-linux-kernel-4.4.55.git] / arch / powerpc / include / asm / exception-64e.h

diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h
index ac13addb849582e7dc450d3e9b7a091c1ddcf4de..51fa43e536b917c08c5870525c9a81063c1448e2 100644 (file)
--- a/arch/powerpc/include/asm/exception-64e.h
+++ b/arch/powerpc/include/asm/exception-64e.h
@@ -37,6 +37,7 @@
  * critical data
  */
 
+#define PACA_EXGDBELL PACA_EXGEN
 
 /* We are out of SPRGs so we save some things in the PACA. The normal
  * exception frame is smaller than the CRIT or MC one though
@@ -45,8 +46,9 @@
 #define EX_CR          (1 * 8)
 #define EX_R10         (2 * 8)
 #define EX_R11         (3 * 8)
-#define EX_R14         (4 * 8)
-#define EX_R15         (5 * 8)
+#define EX_R13         (4 * 8)
+#define EX_R14         (5 * 8)
+#define EX_R15         (6 * 8)
 
 /*
  * The TLB miss exception uses different slots.