#ifdef CONFIG_PPC_BOOK3S_64
BEGIN_FTR_SECTION
- /*
- * Back up the TAR across context switches. Note that the TAR is not
- * available for use in the kernel. (To provide this, the TAR should
- * be backed up/restored on exception entry/exit instead, and be in
- * pt_regs. FIXME, this should be in pt_regs anyway (for debug).)
- */
- mfspr r0,SPRN_TAR
- std r0,THREAD_TAR(r3)
-
/* Event based branch registers */
mfspr r0, SPRN_BESCR
std r0, THREAD_BESCR(r3)
std r0, THREAD_EBBHR(r3)
mfspr r0, SPRN_EBBRR
std r0, THREAD_EBBRR(r3)
-
- /* PMU registers made user read/(write) by EBB */
- mfspr r0, SPRN_SIAR
- std r0, THREAD_SIAR(r3)
- mfspr r0, SPRN_SDAR
- std r0, THREAD_SDAR(r3)
- mfspr r0, SPRN_SIER
- std r0, THREAD_SIER(r3)
- mfspr r0, SPRN_MMCR0
- std r0, THREAD_MMCR0(r3)
- mfspr r0, SPRN_MMCR2
- std r0, THREAD_MMCR2(r3)
- mfspr r0, SPRN_MMCRA
- std r0, THREAD_MMCRA(r3)
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
#endif
ld r0, THREAD_EBBRR(r4)
mtspr SPRN_EBBRR, r0
- /* PMU registers made user read/(write) by EBB */
- ld r0, THREAD_SIAR(r4)
- mtspr SPRN_SIAR, r0
- ld r0, THREAD_SDAR(r4)
- mtspr SPRN_SDAR, r0
- ld r0, THREAD_SIER(r4)
- mtspr SPRN_SIER, r0
- ld r0, THREAD_MMCR0(r4)
- mtspr SPRN_MMCR0, r0
- ld r0, THREAD_MMCR2(r4)
- mtspr SPRN_MMCR2, r0
- ld r0, THREAD_MMCRA(r4)
- mtspr SPRN_MMCRA, r0
-
ld r0,THREAD_TAR(r4)
mtspr SPRN_TAR,r0
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
ld r7,DSCR_DEFAULT@toc(2)
ld r0,THREAD_DSCR(r4)
cmpwi r6,0
+ li r8, FSCR_DSCR
bne 1f
ld r0,0(r7)
-1: cmpd r0,r25
+ b 3f
+1:
+ BEGIN_FTR_SECTION_NESTED(70)
+ mfspr r6, SPRN_FSCR
+ or r6, r6, r8
+ mtspr SPRN_FSCR, r6
+ BEGIN_FTR_SECTION_NESTED(69)
+ mfspr r6, SPRN_HFSCR
+ or r6, r6, r8
+ mtspr SPRN_HFSCR, r6
+ END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
+ b 4f
+ END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
+3:
+ BEGIN_FTR_SECTION_NESTED(70)
+ mfspr r6, SPRN_FSCR
+ andc r6, r6, r8
+ mtspr SPRN_FSCR, r6
+ BEGIN_FTR_SECTION_NESTED(69)
+ mfspr r6, SPRN_HFSCR
+ andc r6, r6, r8
+ mtspr SPRN_HFSCR, r6
+ END_FTR_SECTION_NESTED(CPU_FTR_HVMODE, CPU_FTR_HVMODE, 69)
+ END_FTR_SECTION_NESTED(CPU_FTR_ARCH_207S, CPU_FTR_ARCH_207S, 70)
+4: cmpd r0,r25
beq 2f
mtspr SPRN_DSCR,r0
2: