Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

[firefly-linux-kernel-4.4.55.git] / arch / powerpc / platforms / 85xx / mpc85xx_mds.c

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 1d15a0cd2c82dd2110f27e835ede3cefd30f2bbb..f33662b46b8d31052028c4ff779b5a4d8fc064d1 100644 (file)
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -1,5 +1,6 @@
 /*
- * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
+ * Copyright (C) 2006-2010, 2012 Freescale Semicondutor, Inc.
+ * All rights reserved.
  *
  * Author: Andy Fleming <afleming@freescale.com>
  *
@@ -51,6 +52,7 @@
 #include <asm/qe_ic.h>
 #include <asm/mpic.h>
 #include <asm/swiotlb.h>
+#include <asm/fsl_guts.h>
 #include "smp.h"
 
 #include "mpc85xx.h"
@@ -268,34 +270,27 @@ static void __init mpc85xx_mds_qe_init(void)
        mpc85xx_mds_reset_ucc_phys();
 
        if (machine_is(p1021_mds)) {
-#define MPC85xx_PMUXCR_OFFSET           0x60
-#define MPC85xx_PMUXCR_QE0              0x00008000
-#define MPC85xx_PMUXCR_QE3              0x00001000
-#define MPC85xx_PMUXCR_QE9              0x00000040
-#define MPC85xx_PMUXCR_QE12             0x00000008
-               static __be32 __iomem *pmuxcr;
 
-               np = of_find_node_by_name(NULL, "global-utilities");
+               struct ccsr_guts_85xx __iomem *guts;
 
+               np = of_find_node_by_name(NULL, "global-utilities");
                if (np) {
-                       pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
-
-                       if (!pmuxcr)
-                               printk(KERN_EMERG "Error: Alternate function"
-                                       " signal multiplex control register not"
-                                       " mapped!\n");
-                       else
+                       guts = of_iomap(np, 0);
+                       if (!guts)
+                               pr_err("mpc85xx-rdb: could not map global utilities register\n");
+                       else{
                        /* P1021 has pins muxed for QE and other functions. To
                         * enable QE UEC mode, we need to set bit QE0 for UCC1
                         * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
                         * and QE12 for QE MII management signals in PMUXCR
                         * register.
                         */
-                               setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
-                                                 MPC85xx_PMUXCR_QE3 |
-                                                 MPC85xx_PMUXCR_QE9 |
-                                                 MPC85xx_PMUXCR_QE12);
-
+                               setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+                                                 MPC85xx_PMUXCR_QE(3) |
+                                                 MPC85xx_PMUXCR_QE(9) |
+                                                 MPC85xx_PMUXCR_QE(12));
+                               iounmap(guts);
+                       }
                        of_node_put(np);
                }
 
@@ -434,9 +429,8 @@ machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
 
 static void __init mpc85xx_mds_pic_init(void)
 {
-       struct mpic *mpic = mpic_alloc(NULL, 0,
-                       MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
-                       MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
+       struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+                       MPIC_SINGLE_DEST_CPU,
                        0, 256, " OpenPIC  ");
        BUG_ON(mpic == NULL);