x86, mce: Add boot options for corrected errors

[firefly-linux-kernel-4.4.55.git] / arch / x86 / include / asm / mce.h

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 1156dae295ac22c3f6023a402bae8f6eb1795e4b..540a466e50f52860f410c831d293f57c63120a2d 100644 (file)
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -15,6 +15,7 @@
 #define MCG_EXT_CNT_MASK       0xff0000     /* Number of Extended registers */
 #define MCG_EXT_CNT_SHIFT      16
 #define MCG_EXT_CNT(c)         (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
+#define MCG_SER_P              (1ULL<<24)   /* MCA recovery/new status bits */
 
 #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
 #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
@@ -27,6 +28,15 @@
 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
+#define MCI_STATUS_S    (1ULL<<56)  /* Signaled machine check */
+#define MCI_STATUS_AR   (1ULL<<55)  /* Action required */
+
+/* MISC register defines */
+#define MCM_ADDR_SEGOFF  0     /* segment offset */
+#define MCM_ADDR_LINEAR  1     /* linear address */
+#define MCM_ADDR_PHYS   2      /* physical address */
+#define MCM_ADDR_MEM    3      /* memory address */
+#define MCM_ADDR_GENERIC 7     /* generic */
 
 /* Fields are zero when not available */
 struct mce {
@@ -36,13 +46,19 @@ struct mce {
        __u64 mcgstatus;
        __u64 ip;
        __u64 tsc;      /* cpu time stamp counter */
-       __u64 res1;     /* for future extension */
-       __u64 res2;     /* dito. */
+       __u64 time;     /* wall time_t when error was detected */
+       __u8  cpuvendor;        /* cpu vendor as encoded in system.h */
+       __u8  pad1;
+       __u16 pad2;
+       __u32 cpuid;    /* CPUID 1 EAX */
        __u8  cs;               /* code segment */
        __u8  bank;     /* machine check bank */
-       __u8  cpu;      /* cpu that raised the error */
+       __u8  cpu;      /* cpu number; obsolete; use extcpu now */
        __u8  finished;   /* entry is valid */
-       __u32 pad;
+       __u32 extcpu;   /* linux cpu number that detected the error */
+       __u32 socketid; /* CPU socket ID */
+       __u32 apicid;   /* CPU initial apic ID */
+       __u64 mcgcap;   /* MCGCAP MSR: machine check capabilities of CPU */
 };
 
 /*
@@ -59,7 +75,7 @@ struct mce_log {
        unsigned len;       /* = MCE_LOG_LEN */
        unsigned next;
        unsigned flags;
-       unsigned pad0;
+       unsigned recordlen;     /* length of struct mce */
        struct mce entry[MCE_LOG_LEN];
 };
 
@@ -103,6 +119,8 @@ extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 #define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1)
 
 #ifdef CONFIG_X86_MCE_INTEL
+extern int mce_cmci_disabled;
+extern int mce_ignore_ce;
 void mce_intel_feature_init(struct cpuinfo_x86 *c);
 void cmci_clear(void);
 void cmci_reenable(void);
@@ -125,6 +143,7 @@ static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
 int mce_available(struct cpuinfo_x86 *c);
 
 DECLARE_PER_CPU(unsigned, mce_exception_count);
+DECLARE_PER_CPU(unsigned, mce_poll_count);
 
 void mce_log_therm_throt_event(__u64 status);
 
@@ -142,7 +161,8 @@ enum mcp_flags {
 };
 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
 
-int mce_notify_user(void);
+int mce_notify_irq(void);
+void mce_notify_process(void);
 
 DECLARE_PER_CPU(struct mce, injectm);
 extern struct file_operations mce_chrdev_ops;