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<title>The LLVM Target-Independent Code Generator</title>
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+
+ <style type="text/css">
+ .unknown { background-color: #C0C0C0; text-align: center; }
+ .unknown:before { content: "?" }
+ .no { background-color: #C11B17 }
+ .no:before { content: "N" }
+ .partial { background-color: #F88017 }
+ .yes { background-color: #0F0; }
+ .yes:before { content: "Y" }
+ </style>
+
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<div class="doc_subsection">
- <a name="mcinst">The <tt>MCInst</tt> class</a></li>
+ <a name="mcinst">The <tt>MCInst</tt> class</a>
</div>
<div class="doc_text">
SelectionDAG optimizer is run to clean up redundancies exposed by type
legalization.</li>
- <li><a href="#selectiondag_legalize">Legalize SelectionDAG Types</a> —
- This stage transforms SelectionDAG nodes to eliminate any types that are
- unsupported on the target.</li>
+ <li><a href="#selectiondag_legalize">Legalize SelectionDAG Ops</a> —
+ This stage transforms SelectionDAG nodes to eliminate any operations
+ that are unsupported on the target.</li>
<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> — The
SelectionDAG optimizer is run to eliminate inefficiencies introduced by
meets the needs of your instruction, because it will allow a more concise
description.</p>
+</div>
+
<!-- _______________________________________________________________________ -->
<div class="doc_subsubsection">Mnemonic Aliases</div>
</div>
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">Instruction Aliases</div>
+
+<div class="doc_text">
+
+<p>The most general phase of alias processing occurs while matching is
+happening: it provides new forms for the matcher to match along with a specific
+instruction to generate. An instruction alias has two parts: the string to
+match and the instruction to generate. For example:
+</p>
+
+<div class="doc_code">
+<pre>
+def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8 :$src)>;
+def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)>;
+def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8 :$src)>;
+def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16 :$src)>;
+def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8 :$src)>;
+def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16 :$src)>;
+def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32 :$src)>;
+</pre>
+</div>
+
+<p>This shows a powerful example of the instruction aliases, matching the
+same mnemonic in multiple different ways depending on what operands are present
+in the assembly. The result of instruction aliases can include operands in a
+different order than the destination instruction, and can use an input
+multiple times, for example:</p>
+
+<div class="doc_code">
+<pre>
+def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>;
+def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>;
+def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
+def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
+</pre>
+</div>
+
+<p>This example also shows that tied operands are only listed once. In the X86
+backend, XOR8rr has two input GR8's and one output GR8 (where an input is tied
+to the output). InstAliases take a flattened operand list without duplicates
+for tied operands. The result of an instruction alias can also use immediates
+and fixed physical registers which are added as simple immediate operands in the
+result, for example:</p>
+
+<div class="doc_code">
+<pre>
+// Fixed Immediate operand.
+def : InstAlias<"aad", (AAD8i8 10)>;
+
+// Fixed register operand.
+def : InstAlias<"fcomi", (COM_FIr ST1)>;
+
+// Simple alias.
+def : InstAlias<"fcomi $reg", (COM_FIr RST:$reg)>;
+</pre>
+</div>
+
+
+<p>Instruction aliases can also have a Requires clause to make them
+subtarget specific.</p>
+
+</div>
+
+
<!-- ======================================================================= -->
<div class="doc_subsection" id="na_matching">Instruction Matching</div>
<a name="targetfeatures">Target Feature Matrix</a>
</div>
-<style type="text/css">
- .unknown { background-color: #C0C0C0; text-align: center; }
- .unknown:before { content: "?" }
- .no { background-color: #C11B17 }
- .no:before { content: "N" }
- .partial { background-color: #F88017 }
- .yes { background-color: #00FF00; }
- .yes:before { content: "Y" }
-</style>
-
-
<div class="doc_text">
<p>Note that this table does not include the C backend or Cpp backends, since
<table width="689" border="1" cellspacing="0">
<tr><td></td>
-<td colspan="13" align="center" bgcolor="#ffffcc">Target</td>
+<td colspan="13" align="center" style="background-color:#ffc">Target</td>
</tr>
<tr>
<th>Feature</th>
<td class="no"></td> <!-- CellSPU -->
<td class="no"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
- <td class="unknown"></td> <!-- Mips -->
+ <td class="no"></td> <!-- Mips -->
<td class="no"></td> <!-- PTX -->
<td class="yes"></td> <!-- PowerPC -->
<td class="yes"></td> <!-- Sparc -->
<td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- Blackfin -->
<td class="no"></td> <!-- CellSPU -->
- <td class="no"></td> <!-- MBlaze -->
+ <td class="yes"></td> <!-- MBlaze -->
<td class="no"></td> <!-- MSP430 -->
<td class="no"></td> <!-- Mips -->
<td class="no"></td> <!-- PTX -->
<td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- Blackfin -->
<td class="no"></td> <!-- CellSPU -->
- <td class="no"></td> <!-- MBlaze -->
+ <td class="yes"></td> <!-- MBlaze -->
<td class="no"></td> <!-- MSP430 -->
<td class="no"></td> <!-- Mips -->
<td class="no"></td> <!-- PTX -->
<td class="unknown"></td> <!-- Alpha -->
<td class="yes"></td> <!-- Blackfin -->
<td class="no"></td> <!-- CellSPU -->
- <td class="no"></td> <!-- MBlaze -->
+ <td class="yes"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
- <td class="unknown"></td> <!-- Mips -->
+ <td class="no"></td> <!-- Mips -->
<td class="unknown"></td> <!-- PTX -->
<td class="yes"></td> <!-- PowerPC -->
<td class="unknown"></td> <!-- Sparc -->
<tr>
<td><a href="#feat_jit">jit</a></td>
<td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
- <td class="unknown"></td> <!-- Alpha -->
+ <td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- Blackfin -->
<td class="no"></td> <!-- CellSPU -->
<td class="no"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
- <td class="unknown"></td> <!-- Mips -->
+ <td class="no"></td> <!-- Mips -->
<td class="unknown"></td> <!-- PTX -->
<td class="yes"></td> <!-- PowerPC -->
<td class="unknown"></td> <!-- Sparc -->
<td class="no"></td> <!-- Alpha -->
<td class="no"></td> <!-- Blackfin -->
<td class="no"></td> <!-- CellSPU -->
- <td class="no"></td> <!-- MBlaze -->
+ <td class="yes"></td> <!-- MBlaze -->
<td class="no"></td> <!-- MSP430 -->
<td class="no"></td> <!-- Mips -->
<td class="no"></td> <!-- PTX -->
<td class="no"></td> <!-- CellSPU -->
<td class="no"></td> <!-- MBlaze -->
<td class="unknown"></td> <!-- MSP430 -->
- <td class="unknown"></td> <!-- Mips -->
+ <td class="no"></td> <!-- Mips -->
<td class="unknown"></td> <!-- PTX -->
<td class="yes"></td> <!-- PowerPC -->
<td class="unknown"></td> <!-- Sparc -->