<p>The portion of the instruction definition in bold indicates the pattern used
to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>)
are defined in the <tt>lib/Target/TargetSelectionDAG.td</tt> file.
-"<tt>F4RC</tt>" is the register class of the input and result values.<p>
+"<tt>F4RC</tt>" is the register class of the input and result values.</p>
<p>The TableGen DAG instruction selector generator reads the instruction
patterns in the <tt>.td</tt> file and automatically builds parts of the pattern
from the target code. The most traditional PHI deconstruction
algorithm replaces PHI instructions with copy instructions. That is
the strategy adopted by LLVM. The SSA deconstruction algorithm is
-implemented in n<tt>lib/CodeGen/>PHIElimination.cpp</tt>. In order to
+implemented in <tt>lib/CodeGen/PHIElimination.cpp</tt>. In order to
invoke this pass, the identifier <tt>PHIEliminationID</tt> must be
marked as required in the code of the register allocator.</p>
</pre>
</div>
-<p>can be safely substituted by the single instruction:
+<p>can be safely substituted by the single instruction:</p>
<div class="doc_code">
<pre>
<!-- _______________________________________________________________________ -->
<div class="doc_subsubsection">
- <a name="x86_tt">X86 Target Triples Supported</a>
+ <a name="x86_tt">X86 Target Triples supported</a>
</div>
<div class="doc_text">
</div>
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+ <a name="x86_memory">X86 address spaces supported</a>
+</div>
+
+<div class="doc_text">
+
+<p>x86 has the ability to perform loads and stores to different address spaces
+via the x86 segment registers. A segment override prefix byte on an instruction
+causes the instruction's memory access to go to the specified segment. LLVM
+address space 0 is the default address space, which includes the stack, and
+any unqualified memory accesses in a program. Address spaces 1-255 are
+currently reserved for user-defined code. The GS-segment is represented by
+address space 256. Other x86 segments have yet to be allocated address space
+numbers.
+
+<p>Some operating systems use the GS-segment to implement TLS, so care should be
+taken when reading and writing to address space 256 on these platforms.
+
+</div>
+
<!-- _______________________________________________________________________ -->
<div class="doc_subsubsection">
<a name="x86_names">Instruction naming</a>
<hr>
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<a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
<a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>