new testcase

[oota-llvm.git] / docs / CodeGenerator.html

diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html
index 39eecc1289871a73f01b8ed7205eb92dc6c69b13..da23cf2d99433fcd617202106c6cdaa3b8dc9fbf 100644 (file)
--- a/docs/CodeGenerator.html
+++ b/docs/CodeGenerator.html
@@ -168,17 +168,6 @@ make use of any of the built-in components.  Doing so is not recommended at all,
 but could be required for radically different targets that do not fit into the
 LLVM machine description model: programmable FPGAs for example.</p>
 
-<p><b>Important Note:</b> For historical reasons, the LLVM SparcV9 code
-generator uses almost entirely different code paths than described in this
-document.  For this reason, there are some deprecated interfaces (such as
-<tt>TargetSchedInfo</tt>), which are only used by the
-V9 backend and should not be used by any other targets.  Also, all code in the
-<tt>lib/Target/SparcV9</tt> directory and subdirectories should be considered
-deprecated, and should not be used as the basis for future code generator work.
-The SparcV9 backend is slowly being merged into the rest of the
-target-independent code generators, but this is a low-priority process with no
-predictable completion date.</p>
-
 </div>
 
 <!-- ======================================================================= -->
@@ -444,7 +433,11 @@ href="TableGenFundamentals.html">TableGen</a> description of the register file.
 
 <div class="doc_text">
   <p>
-  TODO
+  <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
+  specific chip set being targeted.  A sub-target informs code generation of 
+  which instructions are supported, instruction latencies and instruction 
+  execution itinerary; i.e., which processing units are used, in what order, and
+  for how long.
   </p>
 </div>
 
@@ -985,7 +978,7 @@ fragment:</p>
   (fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
 </pre>
 
-<p>If a target supports floating pointer multiply-and-add (FMA) operations, one
+<p>If a target supports floating point multiply-and-add (FMA) operations, one
 of the adds can be merged with the multiply.  On the PowerPC, for example, the
 output of the instruction selector might look like this DAG:</p>
 
@@ -1113,7 +1106,7 @@ converted to a list of <a href="#machineinstr">MachineInstr</a>s and the
 Selection DAG is destroyed.
 </p>
 
-<p>Note that this phase is logically seperate from the instruction selection
+<p>Note that this phase is logically separate from the instruction selection
 phase, but is tied to it closely in the code because it operates on
 SelectionDAGs.</p>
 
@@ -1292,7 +1285,7 @@ a character per operand with an optional special size. For example:</p>
   src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /></a>
 
   <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
-  <a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a><br>
+  <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
   Last modified: $Date$
 </address>