Avoid creating a redundant zero APInt.

[oota-llvm.git] / docs / CommandGuide / llc.pod

diff --git a/docs/CommandGuide/llc.pod b/docs/CommandGuide/llc.pod
index 910dfad450f594ced6970a73cac2bd23095eaffd..f5fd34f01ab51eaa192207c220fcdc92830c5127 100644 (file)
--- a/docs/CommandGuide/llc.pod
+++ b/docs/CommandGuide/llc.pod
@@ -10,18 +10,18 @@ B<llc> [I<options>] [I<filename>]
 
 =head1 DESCRIPTION
 
-The B<llc> command compiles LLVM bytecode into assembly language for a
+The B<llc> command compiles LLVM bitcode into assembly language for a
 specified architecture.  The assembly language output can then be passed through
 a native assembler and linker to generate a native executable.
 
 The choice of architecture for the output assembly code is automatically
-determined from the input bytecode file, unless the B<-march> option is used to
+determined from the input bitcode file, unless the B<-march> option is used to
 override the default.
 
 =head1 OPTIONS
 
-If I<filename> is - or omitted, B<llc> reads LLVM bytecode from standard input.
-Otherwise, it will read LLVM bytecode from I<filename>.
+If I<filename> is - or omitted, B<llc> reads LLVM bitcode from standard input.
+Otherwise, it will read LLVM bitcode from I<filename>.
 
 If the B<-o> option is omitted, then B<llc> will send its output to standard
 output if the input is from standard input.  If the B<-o> option specifies -,
@@ -46,11 +46,31 @@ Print a summary of command line options.
 Overwrite output files. By default, B<llc> will refuse to overwrite
 an output file which already exists.
 
+=item B<-mtriple>=I<target triple>
+
+Override the target triple specified in the input bitcode file with the 
+specified string.
+
 =item B<-march>=I<arch>
 
 Specify the architecture for which to generate assembly, overriding the target
-encoded in the bytecode file.  See the output of B<llc --help> for a list of
-valid architectures.
+encoded in the bitcode file.  See the output of B<llc --help> for a list of
+valid architectures.  By default this is inferred from the target triple or
+autodetected to the current architecture.
+
+=item B<-mcpu>=I<cpuname>
+
+Specify a specific chip in the current architecture to generate code for.
+By default this is inferred from the target triple and autodetected to 
+the current architecture.  For a list of available CPUs, use:
+B<llvm-as E<lt> /dev/null | llc -march=xyz -mcpu=help>
+
+=item B<-mattr>=I<a1,+a2,-a3,...>
+
+Override or control specific attributes of the target, such as whether SIMD
+operations are enabled or not.  The default set of attributes is set by the
+current CPU.  For a list of available attributes, use:
+B<llvm-as E<lt> /dev/null | llc -march=xyz -mattr=help>
 
 =item B<--disable-fp-elim>
 
@@ -155,20 +175,6 @@ syntax.
 
 =back
 
-=head2 SPARCV9-specific Options
-
-=over
-
-=item B<--disable-peephole>
-
-Disable peephole optimization pass.
-
-=item B<--disable-sched>
-
-Disable local scheduling pass.
-
-=back
-
 =head1 EXIT STATUS
 
 If B<llc> succeeds, it will exit with 0.  Otherwise, if an error occurs,
@@ -180,6 +186,6 @@ L<lli|lli>
 
 =head1 AUTHORS
 
-Maintained by the LLVM Team (L<http://llvm.cs.uiuc.edu>).
+Maintained by the LLVM Team (L<http://llvm.org>).
 
 =cut