=item B<-march>=I<arch>
Specify the architecture for which to generate assembly, overriding the target
-encoded in the bitcode file. See the output of B<llc --help> for a list of
+encoded in the bitcode file. See the output of B<llc -help> for a list of
valid architectures. By default this is inferred from the target triple or
autodetected to the current architecture.
Disable optimizations that may increase floating point precision.
-=item B<-enable-finite-only-fp-math>
+=item B<-enable-no-infs-fp-math>
-Enable optimizations that assumes only finite floating point math. That is,
-there is no NAN or Inf values.
+Enable optimizations that assume no Inf values.
+
+=item B<-enable-no-nans-fp-math>
+
+Enable optimizations that assume no NAN values.
=item B<-enable-unsafe-fp-math>
Make the -lowerinvoke pass insert expensive, but correct, EH code.
-=item B<-enable-eh>
+=item B<-jit-enable-eh>
-Exception handling should be emitted.
+Exception handling should be enabled in the just-in-time compiler.
=item B<-join-liveintervals>
=item B<-regalloc>=I<allocator>
-Register allocator to use: (default = linearscan)
+Register allocator to use (default=linearscan)
=bigblock: Big-block register allocator
=linearscan: linear scan register allocator =local - local register allocator
=item B<-spiller>
-Spiller to use: (default: local)
+Spiller to use (default=local)
=simple: simple spiller
=local: local spiller