Fix the syntax of insertvalue in the example.

[oota-llvm.git] / docs / CommandGuide / lli.pod

diff --git a/docs/CommandGuide/lli.pod b/docs/CommandGuide/lli.pod
index 708cae2bb109fde0486883782c7ec951d05462ec..e9fdf74fe53ea7e849c8741717df34da089ff7ba 100644 (file)
--- a/docs/CommandGuide/lli.pod
+++ b/docs/CommandGuide/lli.pod
@@ -22,14 +22,28 @@ program from standard input.
 The optional I<args> specified on the command line are passed to the program as
 arguments.
 
-=head1 OPTIONS
+=head1 GENERAL OPTIONS
 
 =over
 
+=item B<-fake-argv0>=I<executable>
+
+Override the C<argv[0]> value passed into the executing program.
+
+=item B<-force-interpreter>=I<{false,true}>
+
+If set to true, use the interpreter even if a just-in-time compiler is available
+for this architecture. Defaults to false.
+
 =item B<-help>
 
 Print a summary of command line options.
 
+=item B<-load>=I<puginfilename>
+
+Causes B<lli> to load the plugin (shared object) named I<pluginfilename> and use
+it for optimization.
+
 =item B<-stats>
 
 Print statistics from the code-generation passes. This is only meaningful for
@@ -40,6 +54,16 @@ the just-in-time compiler, at present.
 Record the amount of time needed for each code-generation pass and print it to
 standard error.
 
+=item B<-version>
+
+Print out the version of B<lli> and exit without doing anything else.
+
+=back 
+
+=head1 TARGET OPTIONS
+
+=over 
+
 =item B<-mtriple>=I<target triple>
 
 Override the target triple specified in the input bitcode file with the 
@@ -67,19 +91,26 @@ operations are enabled or not.  The default set of attributes is set by the
 current CPU.  For a list of available attributes, use:
 B<llvm-as E<lt> /dev/null | llc -march=xyz -mattr=help>
 
-=item B<-fake-argv0>=I<executable>
+=back
 
-Override the C<argv[0]> value passed into the executing program.
 
-=item B<-force-interpreter>=I<{false,true}>
+=head1 FLOATING POINT OPTIONS
 
-If set to true, use the interpreter even if a just-in-time compiler is available
-for this architecture. Defaults to false.
+=over 
 
-=item B<-load>=I<puginfilename>
+=item B<-disable-excess-fp-precision>
 
-Causes B<lli> to load the plugin (shared object) named I<pluginfilename> and use
-it for optimization.
+Disable optimizations that may increase floating point precision.
+
+=item B<-enable-finite-only-fp-math>
+
+Enable optimizations that assumes only finite floating point math. That is,
+there is no NAN or Inf values.
+
+=item B<-enable-unsafe-fp-math>
+
+Causes B<lli> to enable optimizations that may decrease floating point
+precision.
 
 =item B<-soft-float>
 
@@ -88,6 +119,87 @@ equivalent hardware instructions.
 
 =back
 
+=head1 CODE GENERATION OPTIONS
+
+=over
+
+=item B<-code-model>=I<model>
+
+Choose the code model from:
+
+    default: Target default code model
+    small: Small code model
+    kernel: Kernel code model
+    medium: Medium code model
+    large: Large code model
+
+=item B<-disable-post-RA-scheduler>
+
+Disable scheduling after register allocation.
+
+=item B<-disable-spill-fusing>
+
+Disable fusing of spill code into instructions.
+
+=item B<-enable-correct-eh-support> 
+
+Make the -lowerinvoke pass insert expensive, but correct, EH code.
+
+=item B<-enable-eh> 
+
+Exception handling should be emitted.
+
+=item B<-join-liveintervals> 
+
+Coalesce copies (default=true).
+
+=item B<-nozero-initialized-in-bss>
+Don't place zero-initialized symbols into the BSS section.
+
+=item B<-pre-RA-sched>=I<scheduler>
+
+Instruction schedulers available (before register allocation):
+
+    =default: Best scheduler for the target 
+    =none: No scheduling: breadth first sequencing 
+    =simple: Simple two pass scheduling: minimize critical path and maximize processor utilization 
+    =simple-noitin: Simple two pass scheduling: Same as simple except using generic latency 
+    =list-burr: Bottom-up register reduction list scheduling 
+    =list-tdrr: Top-down register reduction list scheduling 
+    =list-td: Top-down list scheduler -print-machineinstrs - Print generated machine code
+
+=item B<-regalloc>=I<allocator>
+
+Register allocator to use: (default = linearscan)
+
+    =bigblock: Big-block register allocator 
+    =linearscan: linear scan register allocator =local -   local register allocator 
+    =simple: simple register allocator 
+
+=item B<-relocation-model>=I<model> 
+
+Choose relocation model from:
+
+    =default: Target default relocation model 
+    =static: Non-relocatable code =pic -   Fully relocatable, position independent code 
+    =dynamic-no-pic: Relocatable external references, non-relocatable code 
+
+=item B<-spiller>
+
+Spiller to use: (default: local) 
+
+    =simple: simple spiller 
+    =local: local spiller 
+
+=item B<-x86-asm-syntax>=I<syntax>
+
+Choose style of code to emit from X86 backend: 
+
+    =att: Emit AT&T-style assembly 
+    =intel: Emit Intel-style assembly
+
+=back
+
 =head1 EXIT STATUS
 
 If B<lli> fails to load the program, it will exit with an exit code of 1.