a fast memory error detector.</li>
<li><a href="CodeGenerator.html#machineinstrbundle">MachineInstr Bundles</a>,
Support to model instruction bundling / packing.</li>
+ <li><a href="#armintegratedassembler">ARM Integrated Assembler</a>,
+ A full featured assembler and direct-to-object support for ARM.</li>
<li>....</li>
</ul>
<ul>
<li>IR support for half float</li>
- <li>IR support for vectors of pointers, including vector GEPs.</li>
+ <li>IR support for vectors of pointers, including vector GEPs.</li>
+ <li>Module flags have been introduced. They convey information about the
+ module as a whole to LLVM subsystems.</li>
+ <li>Loads can now have range metadata attached to them to describe the
+ possible values being loaded.</li>
<li>....</li>
</ul>
</div>
optimizers:</p>
<ul>
+ <li>The loop unroll pass now is able to unroll loops with run-time trip counts.
+ This feature is turned off by default, and is enabled with the
+ <code>-unroll-runtime</code> flag.</li>
+ <li>A new basic-block autovectorization pass is available. Pass
+ <code>-vectorize</code> to run this pass along with some associated
+ post-vectorization cleanup passes.</li>
<li>....</li>
</ul>
<div>
-<p>We have changed the way that the Type Legalizer legalizes vectors.
- The type legalizer now attempts to promote integer elements.
- This enabled the implementation of vector-select.
- Additionally, we see a performance boost on workloads which use vectors of chars and shorts, since they are now promoted
- to 32-bit types, which are better supported by the SIMD instruction set.
- Floating point types are still widened as before.</p>
+<p>We have changed the way that the Type Legalizer legalizes vectors. The type
+ legalizer now attempts to promote integer elements. This enabled the
+ implementation of vector-select. Additionally, we see a performance boost on
+ workloads which use vectors of chars and shorts, since they are now promoted
+ to 32-bit types, which are better supported by the SIMD instruction set.
+ Floating point types are still widened as before.</p>
<p>We have put a significant amount of work into the code generator
<ul>
<li>TableGen can now synthesize register classes that are only needed to
- represent combinations of constraints from instructions and sub-registers.
- The synthetic register classes inherit most of their properties form their
- closest user-defined super-class.</li>
+ represent combinations of constraints from instructions and sub-registers.
+ The synthetic register classes inherit most of their properties form their
+ closest user-defined super-class.</li>
+ <li><code>MachineRegisterInfo</code> now allows the reserved registers to be
+ frozen when register allocation starts. Target hooks should use the
+ <code>MRI->canReserveReg(FramePtr)</code> method to avoid accidentally
+ disabling frame pointer elimination during register allocation.</li>
+ <li>A new kind of <code>MachineOperand</code> provides a compact
+ representation of large clobber lists on call instructions. The register
+ mask operand references a bit mask of preserved registers. Everything else
+ is clobbered.</li>
</ul>
+
+<p> We added new TableGen infrastructure to support bundling for
+ Very Long Instruction Word (VLIW) architectures. TableGen can now
+ automatically generate a deterministic finite automaton from a VLIW
+ target's schedule description which can be queried to determine
+ legal groupings of instructions in a bundle.</p>
+
+<p> We have added a new target independent VLIW packetizer based on the
+ DFA infrastructure to group machine instructions into bundles.</p>
+
</div>
<!--=========================================================================-->
<ul>
<li>Bug fixes and improved support for AVX1</li>
<li>Support for AVX2 (still incomplete at this point)</li>
- <li>....</li>
+ <li>Call instructions use the new register mask operands for faster compile
+ times and better support for different calling conventions. The old WINCALL
+ instructions are no longer needed.</li>
+ <li>DW2 Exception Handling is enabled on Cygwin and MinGW.</li>
+ <li>Support for implicit TLS model used with MS VC runtime</li>
</ul>
</div>
<ul>
<li>The constant island pass now supports basic block and constant pool entry
- alignments greater than 4 bytes.</li> </ul>
-</div>
+ alignments greater than 4 bytes.</li>
+ <li>On Darwin, the ARM target now has a full-featured integrated assembler.
+ </li>
+</ul>
+
+<h4>
+<a name="armintegratedassembler">ARM Integrated Assembler</a>
+</h4>
+<div>
+<p>The ARM target now includes a full featured macro assembler, including
+direct-to-object module support for clang. The assembler is currently enabled
+by default for Darwin only pending testing and any additional necessary
+platform specific support for Linux.</p>
+
+<p>Full support is included for Thumb1, Thumb2 and ARM modes, along with
+subtarget and CPU specific extensions for VFP2, VFP3 and NEON.</p>
+<p>The assembler is Unified Syntax only (see ARM Architecural Reference Manual
+for details). While there is some, and growing, support for pre-unfied (divided)
+syntax, there are still significant gaps in that support.</p>
+</div>
+</div>
<!--=========================================================================-->
<h3>
<a name="MIPS">MIPS Target Improvements</a>
<div>
+<p>Support for Qualcomm's Hexagon VLIW processor has been added.</p>
+
<ul>
<li>....</li>
from the previous release.</p>
<ul>
-<li>LLVM 3.1 removes support for reading LLVM 2.9 bitcode files. Going forward,
- we aim for all future versions of LLVM to read bitcode files and .ll files
- produced by LLVM 3.0 and later.</li>
+ <li>LLVM 3.1 removes support for reading LLVM 2.9 bitcode files. Going
+ forward, we aim for all future versions of LLVM to read bitcode files and
+ <tt>.ll</tt> files produced by LLVM 3.0 and later.</li>
+ <li>The <tt>unwind</tt> instruction is now gone. With the introduction of the
+ new exception handling system in LLVM 3.0, the <tt>unwind</tt> instruction
+ became obsolete.</li>
<li>....</li>
</ul>
<p>In addition, many APIs have changed in this release. Some of the major
LLVM API changes are:</p>
+<ul>
+ <li>Target specific options have been moved from global variables to members
+ on the new <code>TargetOptions</code> class, which is local to each
+ <code>TargetMachine</code>. As a consequence, the associated flags will
+ no longer be accepted by <tt>clang -mllvm</tt>. This includes:
+<ul>
+<li><code>llvm::PrintMachineCode</code></li>
+<li><code>llvm::NoFramePointerElim</code></li>
+<li><code>llvm::NoFramePointerElimNonLeaf</code></li>
+<li><code>llvm::DisableFramePointerElim(const MachineFunction &)</code></li>
+<li><code>llvm::LessPreciseFPMADOption</code></li>
+<li><code>llvm::LessPrecideFPMAD()</code></li>
+<li><code>llvm::NoExcessFPPrecision</code></li>
+<li><code>llvm::UnsafeFPMath</code></li>
+<li><code>llvm::NoInfsFPMath</code></li>
+<li><code>llvm::NoNaNsFPMath</code></li>
+<li><code>llvm::HonorSignDependentRoundingFPMathOption</code></li>
+<li><code>llvm::HonorSignDependentRoundingFPMath()</code></li>
+<li><code>llvm::UseSoftFloat</code></li>
+<li><code>llvm::FloatABIType</code></li>
+<li><code>llvm::NoZerosInBSS</code></li>
+<li><code>llvm::JITExceptionHandling</code></li>
+<li><code>llvm::JITEmitDebugInfo</code></li>
+<li><code>llvm::JITEmitDebugInfoToDisk</code></li>
+<li><code>llvm::GuaranteedTailCallOpt</code></li>
+<li><code>llvm::StackAlignmentOverride</code></li>
+<li><code>llvm::RealignStack</code></li>
+<li><code>llvm::DisableJumpTables</code></li>
+<li><code>llvm::EnableFastISel</code></li>
+<li><code>llvm::getTrapFunctionName()</code></li>
+<li><code>llvm::EnableSegmentedStacks</code></li>
+</ul></li>
+ <li>The MDBuilder class has been added to simplify the creation of
+ metadata.</li>
+ <li>....</li>
+</ul>
+
+</div>
+
+<!--=========================================================================-->
+<h3>
+<a name="tools_changes">Tools Changes</a>
+</h3>
+
+<div>
+
+<p>In addition, some tools have changed in this release. Some of the changes
+ are:</p>
+
+
+<ul>
+ <li>llvm-stress is a command line tool for generating random .ll files to fuzz
+ different LLVM components. </li>
+ <li>....</li>
+</ul>
+
<ul>
<li>....</li>
</ul>
projects / oota-llvm.git / blobdiff